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NBC12429AMNR4G Datasheet(PDF) 7 Page - ON Semiconductor |
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NBC12429AMNR4G Datasheet(HTML) 7 Page - ON Semiconductor |
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7 / 22 page  NBC12429, NBC12429A http://onsemi.com 7 Table 8. AC CHARACTERISTICS (VCC = 3.125 V to 5.25 V; TA = 0°C to 70°C (NBC12429), TA = −40°C to 85°C (NBC12429A)) (Note 6) Symbol Characteristic Condition Min Max Unit FMAXI Maximum Input Frequency S_CLOCK Xtal Oscillator (Note 7) 10 10 20 MHz FMAXO Maximum Output Frequency VCO (Internal) FOUT 200 25 400 400 MHz tjitter(pd) Period Jitter @ 3.3 V 10000 WFMS (See Table 13 for Typical Values) 25 MHz < fOUT < 100 MHz, M = 200 25 MHz < fOUT < 100 MHz, M = 300 25 MHz < fOUT < 100 MHz, M = 400 100 MHz < fOUT < 400 MHz, M = 200 100 MHz < fOUT < 400 MHz, M = 300 100 MHz < fOUT < 400 MHz, M = 400 25 9.0 6.0 9.0 5.0 4.0 psRMS 25 MHz < fOUT < 100 MHz, M = 200 25 MHz < fOUT < 100 MHz, M = 300 25 MHz < fOUT < 100 MHz, M = 400 100 MHz < fOUT < 400 MHz, M = 200 100 MHz < fOUT < 400 MHz, M = 300 100 MHz < fOUT < 400 MHz, M = 400 146 71 53 125 60 54 psPP Period Jitter @ 5.0 V 10000 WFMS (See Table 13 for Typical Values) 25 MHz < fOUT < 100 MHz, M = 200 25 MHz < fOUT < 100 MHz, M = 300 25 MHz < fOUT < 100 MHz, M = 400 100 MHz < fOUT < 400 MHz, M = 200 100 MHz < fOUT < 400 MHz, M = 300 100 MHz < fOUT < 400 MHz, M = 400 25 9.0 6.0 10 6.0 5.0 psRMS 25 MHz < fOUT < 100 MHz, M = 200 25 MHz < fOUT < 100 MHz, M = 300 25 MHz < fOUT < 100 MHz, M = 400 100 MHz < fOUT < 400 MHz, M = 200 100 MHz < fOUT < 400 MHz, M = 300 100 MHz < fOUT < 400 MHz, M = 400 168 69 57 133 49 108 psPP tjitter(cyc−cyc) Cycle−to−Cycle @ 3.3 V 1000 WFMS (See Table 13 for Typical Values) 25 MHz < fOUT < 100 MHz, M = 200 25 MHz < fOUT < 100 MHz, M = 300 25 MHz < fOUT < 100 MHz, M = 400 100 MHz < fOUT < 400 MHz, M = 200 100 MHz < fOUT < 400 MHz, M = 300 100 MHz < fOUT < 400 MHz, M = 400 20 11 8.0 17 10 9.0 psRMS 25 MHz < fOUT < 100 MHz, M = 200 25 MHz < fOUT < 100 MHz, M = 300 25 MHz < fOUT < 100 MHz, M = 400 100 MHz < fOUT < 400 MHz, M = 200 100 MHz < fOUT < 400 MHz, M = 300 100 MHz < fOUT < 400 MHz, M = 400 150 105 77 208 94 89 psPP Cycle−to−Cycle @ 5.0 V 1000 WFMS (See Table 13 for Typical Values) 25 MHz < fOUT < 100 MHz, M = 200 25 MHz < fOUT < 100 MHz, M = 300 25 MHz < fOUT < 100 MHz, M = 400 100 MHz < fOUT < 400 MHz, M = 200 100 MHz < fOUT < 400 MHz, M = 300 100 MHz < fOUT < 400 MHz, M = 400 25 12 8.0 18 11 10 psRMS 25 MHz < fOUT < 100 MHz, M = 200 25 MHz < fOUT < 100 MHz, M = 300 25 MHz < fOUT < 100 MHz, M = 400 100 MHz < fOUT < 400 MHz, M = 200 100 MHz < fOUT < 400 MHz, M = 300 100 MHz < fOUT < 400 MHz, M = 400 192 131 76 164 128 186 psPP tLOCK Maximum PLL Lock Time 10 ms NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. FOUT/FOUT outputs are terminated through a 50 W resistor to VCC − 2.0 V. 7. 10 MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at higher frequencies when used as a test clock in TEST_MODE 6. |
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