NBC12439FAG datasheet(8/21 Pages) ONSEMI

Part #	NBC12439FAG

Description	3.3V/5V Programmable PLL Synthesized Clock Generator

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NBC12439, NBC12439A

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FUNCTIONAL DESCRIPTION

The internal oscillator uses the external quartz crystal as

the basis of its frequency reference. The output of the

reference oscillator is divided by 2 before being sent to the

phase detector. With a 16 MHz crystal, this provides a

reference frequency of 8 MHz. Although this data sheet

illustrates functionality only for a 16 MHz crystal, Table 9,

any crystal in the 10 − 20 MHz range can be used, Table 11.

The VCO within the PLL operates over a range of 400 to

800 MHz. Its output is scaled by a divider, M divider, that is

configured by either the serial or parallel interfaces. The

output of this loop divider is also applied to the phase

detector.

The phase detector and the loop filter force the VCO

output frequency to be M times the reference frequency by

adjusting the VCO control voltage. Note that for some

values of M (either too high or too low), the PLL will not

achieve loop lock.

The output of the VCO is also passed through an output

divider before being sent to the PECL output driver. This

N output divider is configured through either the serial or the

parallel interfaces and can provide one of four division ratios

(1, 2, 4, or 8). This divider extends the performance of the

part while providing a 50% duty cycle.

The output driver is driven differentially from the output

divider and is capable of driving a pair of transmission lines

terminated into 50

W to VCC − 2.0 V. The positive reference

for the output driver and the internal logic is separated from

the power supply for the phase−locked loop to minimize

noise induced jitter.

The configuration logic has two sections: serial and

parallel. The parallel interface uses the values at the M[6:0]

and N[1:0] inputs to configure the internal counters.

Normally upon system reset, the P_LOAD input is held

LOW until sometime after power becomes valid. On the

LOW−to−HIGH transition of P_LOAD, the parallel inputs

are captured. The parallel interface has priority over the

serial interface. Internal pullup resistors are provided on the

M[6:0] and N[1:0] inputs to reduce component count in the

application of the chip.

The serial interface logic is implemented with a fourteen

bit shift register scheme. The register shifts once per rising

edge of the S_CLOCK input. The serial input S_DATA must

meet setup and hold timing as specified in the AC

Characteristics section of this document. With P_LOAD

held high, the configuration latches will capture the value of

the shift register on the HIGH−to−LOW edge of the

S_LOAD input. See the programming section for more

information.

The TEST output reflects various internal node values and

is controlled by the T[2:0] bits in the serial data stream. See

the programming section for more information.

Table 9. Programming VCO Frequency Function Table with 16 MHz Crystal

VCO

Frequency (MHz)

M Count Divisor

64

32

16

8

4

2

1

M6

M5

M4

M3

M2

M1

M0

400

25

0

1

0

1

416

26

0

1

0

1

0

432

27

0

1

0

1

448

28

0

1

0

•

752

47

0

1

0

1

768

48

0

1

0

784

49

0

1

0

1

800

50

0

1

0

1

0

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