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NBSG53A Datasheet(PDF) 2 Page - ON Semiconductor

Part No. NBSG53A
Description  2.5 V/3.3 V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NBSG53A Datasheet(HTML) 2 Page - ON Semiconductor

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NBSG53A
http://onsemi.com
2
VTD
D
D
VTD
VCC
R
SEL OLS
VEE
Q
Q
VCC
VTCLK
CLK
CLK
VTCLK
56
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NBSG53A
Exposed Pad
(EP)
Figure 1. QFN−16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
VTCLK
Internal 50
W Termination Pin. See Table 4.
2
CLK
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input.
3
CLK
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input.
4
VTCLK
Internal 50
W Termination Pin. See Table 4.
5
VTD
Internal 50
W termination pin. See Table 4.
6
D
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input.
7
D
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input.
8
VTD
Internal 50
W Termination Pin. See Table 4.
9,16
VCC
Positive Supply Voltage
10
Q
RSECL Output
NonInverted Differential Output. Typically Terminated with 50
W Resistor to
VTT = VCC − 2 V.
11
Q
RSECL Output
Inverted Differential Output. Typically Terminated with 50
W Resistor to
VTT = VCC − 2 V.
12
VEE
Negative Supply Voltage
13
OLS*
Input
Input Pin for the Output Level Select (OLS). See Table 2.
14
SEL
LVECL, LVCMOS,
LVTTL Input
Select Logic Input. Internal 75 k
W to VEE.
15
R
LVECL, LVCMOS,
LVTTL Input
Reset D Flip-Flop. Internal 75 k
W to VEE.
EP
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to
a heat-sinking conduit. The pad is not electrically connected to the die but may be
electrically and thermally connected to VEE on the PC board.
1. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad (EP) on
package bottom (see case drawing) must be attached to a heat-sinking conduit.
2. In the differential configuration when the input termination pins (VTD, VTD, VTCLK, VTCLK) are connected to a common termination voltage,
and if no signal is applied then the device will be susceptible to self-oscillation.
3. When an output level of 400 mV is desired and VCC − VEE > 3.0 V, 2 kW resistor should be connected from OLS pin to VEE.


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