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NBSG53A Datasheet(PDF) 9 Page - ON Semiconductor

Part No. NBSG53A
Description  2.5 V/3.3 V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NBSG53A Datasheet(HTML) 9 Page - ON Semiconductor

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NBSG53A
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9
Table 10. AC CHARACTERISTICS
(VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V)
Symbol
Characteristic
−40
°C
25
°C
85
°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fmax
Maximum Input Clock Frequency
(See Figures 3, 5, 7, 9, and 10)
DFF
(See Figures 4, 6, 8, 9, and 10)
(Note 25)
DIV/2
8
10
8
10
8
10
GHz
tPLH,
tPHL
Propagation Delay to Output Differential
(Note 29)
CLK
→Q, Q
SEL
→Q, Q
R
→Q, Q DIN/2
DFF
150
100
215
195
215
190
280
270
285
280
375
345
150
100
215
195
215
190
280
270
285
280
375
345
150
100
215
195
215
190
280
270
285
280
375
345
ps
tSKEW
Duty Cycle Skew (Notes 26 and 28) DFF
5
20
5
20
5
20
ps
tJITTER
RMS Random Clock Jitter
fin v 8 GHz
(See Figures 3 and 5) (Note 25)
Peak−to−Peak Data Dependent Jitter
fin = 8 Gb/s
0.5
TBD
1
0.5
TBD
1
0.5
TBD
1
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 27)
75
2600
75
2600
75
2600
mV
tr
tf
Output Rise/Fall Times (20% − 80%)
@ 1 GHz
Q, Q
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
**(OLS = VEE)
28
15
25
20
40
40
35
35
65
65
65
65
28
15
25
20
40
40
35
35
65
65
65
65
28
15
25
20
40
40
35
35
65
65
65
65
ps
ts
Setup Time
D
→CLK
30
14
30
10
30
13
ps
th
Hold Time
D
→CLK
25
12
25
7
25
0
ps
trr
Reset Recovery
DFF, DIV/2
40
9
40
12
40
10
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
25. Measured using a 500 mV source, 50% duty cycle clock source. Repetitive 1010 input data pattern. All outputs loaded with 50
W to
VCC − 2.0 V. Input edge rates is 40 ps (20% − 80%).
26. See Figure 18. tSKEW = |tPLH − tPHL| for a nominal 50% differential clock input waveform.
27. VINPP (MAX) cannot exceed VCC − VEE (Applicable only when VCC − VEE < 2600 mV).
28. See Figure 9. Duty Cycle % vs. Frequency.
29. For all OLS Configuration.
**When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE.


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