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LM2409 Datasheet(PDF) 5 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. LM2409
Description  Monolithic Triple 9.5 ns CRT Driver
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com

LM2409 Datasheet(HTML) 5 Page - National Semiconductor (TI)

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Application Hints (Continued)
Referring to
Figure 9, there are three components (R1, R2
and L1) that can be adjusted to optimize the transient re-
sponse of the application circuit. Increasing the values of R1
and R2 will slow the circuit down while decreasing over-
shoot. Increasing the value of L1 will speed up the circuit as
well as increase overshoot. It is very important to use induc-
tors with very high self-resonant frequencies, preferably
above 300 MHz. Ferrite core inductors from J.W. Miller Mag-
netics (part # 78FR82K) were used for optimizing the perfor-
mance of the device in the NSC application board. The val-
ues shown in
Figure 9 can be used as a good starting point
for the evaluation of the LM2409. The NSC demo board also
has a position open to add a resistor in parallel with L1. This
resistor can be used to help control overshoot. Using vari-
able resistors for R1 and the parallel resistor will simplify
finding the values needed for optimum performance in a
given application. Once the optimum values are determined
the variable resistors can be replaced with fixed values.
Figure 8 shows the effect of increased load capacitance on
the speed of the device. This demonstrates the importance
of knowing the load capacitance in the application.
Figure 7 shows the variation in rise and fall times when the
output offset of the device is varied from 40 V
DC to 50 VDC.
The rise time shows a maximum variation relative to the cen-
ter data point (45 V
DC) of about 21%. The fall time shows a
variation of about 3% relative to the center data point.
Figure 4 shows the performance of the LM2409 in the test
circuit shown in
Figure 2 as a function of case temperature.
The figure shows that the rise time of the LM2409 increases
by approximately 3% as the case temperature increases
from 50˚C to 100˚C. This corresponds to a speed degrada-
tion of 0.6% for every 10˚C rise in case temperature. The fall
time increases by approximately 3% which corresponds to a
speed degradation of 0.6% for every 10˚C rise in case tem-
Figure 6 shows the maximum power dissipation of the
LM2409 vs Frequency when all three channels of the device
are driving an 8 pF load with a 40 V
p-p alternating one pixel
on, one pixel off signal. The graph assumes a 72% active
time (device operating at the specified frequency) which is
typical in a monitor application. The other 28% of the time
the device is assumed to be sitting at the black level (65V in
this case). This graph gives the designer the information
needed to determine the heat sink requirement for the appli-
cation. The designer should note that if the load capacitance
is increased the AC component of the total power dissipation
will also increase.
The LM2409 case temperature must be maintained below
If the maximum expected ambient temperature is 70˚C and
the maximum power dissipation is 3.4W (from
Figure 6,40
MHz bandwidth) then a maximum heat sink thermal resis-
tance can be calculated:
This example assumes a capacitive load of 8 pF and no re-
sistive load.
A typical application of the LM2409 is shown in
Figure 10.
Used in conjunction with an LM1279, a complete video chan-
nel from monitor input to CRT cathode can be achieved. Per-
formance is ideal for 1024 x 768 resolution displays with
pixel clock frequencies up to 75 MHz.
Figure 10 is the sche-
matic for the NSC demonstration board that can be used to
evaluate the LM1279/2409 combination in a monitor.
For optimum performance, an adequate ground plane, isola-
tion between channels, good supply bypassing and minimiz-
ing unwanted feedback are necessary. Also, the length of the
signal traces from the preamplifier to the LM2409 and from
the LM2409 to the CRT cathode should be as short as pos-
sible. The following references are recommended:
Ott, Henry W., “Noise Reduction Techniques in Electronic
Systems”, John Wiley & Sons, New York, 1976.
“Guide to CRT Video Design”, National Semiconductor Appli-
cation Note 861.
“Video Amplifier Design for Computer Monitors”, National
Semiconductor Application Note 1013.
Robert A.,
“Troubleshooting Analog
Butterworth-Heinemann, 1991.
Because of its high small signal bandwidth, the part may os-
cillate in a monitor if feedback occurs around the video chan-
nel through the chassis wiring. To prevent this, leads to the
video amplifier input circuit should be shielded, and input cir-
cuit wiring should be spaced as far as possible from output
circuit wiring.
Figure 11 shows routing and component placement on the
NSC LM1279/2409 demonstration board. The schematic of
the board is shown in
Figure 10. This board provides a good
example of a layout that can be used as a guide for future
layouts. Note the location of the following components:
C55 —V
CC bypass capacitor, located very close to pin 6
and ground pins
C43, C44 —V
BB bypass capacitors, located close to pin
10 and ground
C53–C55 —V
CC bypass capacitors, near LM2409 and
CC clamp diodes. Very important for arc protection.
The routing of the LM2409 outputs to the CRT is very critical
to achieving optimum performance.
Figure 12 shows the
routing and component placement from pin 1 of the LM2409
to the blue cathode. Note that the components are placed so
that they almost line up from the output pin of the LM2409 to
the blue cathode pin of the CRT connector. This is done to
minimize the length of the video path between these two
components. Note also that D14, D15, R29 and D13 are
placed to minimize the size of the video nodes that they are
attached to. This minimizes parasitic capacitance in the
video path and also enhances the effectiveness of the pro-
tection diodes. The anode of protection diode D14 is con-
nected directly to a section of the the ground plane that has
a short and direct path to the LM2409 ground pins. The cath-
ode of D15 is connected to V
CC very close to decoupling ca-
pacitor C55 (see
Figure 12) which is connected to the same
section of the ground plane as D14. The diode placement
and routing is very important for minimizing the voltage

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