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NB100LVEP91 Datasheet(PDF) 1 Page - ON Semiconductor |
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NB100LVEP91 Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 11 page © Semiconductor Components Industries, LLC, 2016 August, 2016 − Rev. 19 1 Publication Order Number: NB100LVEP91/D NB100LVEP91 2.5 V/3.3 V Any Level Positive Input to -2.5 V/-3.3 V LVNECL Output Translator Description The NB100LVEP91 is a triple any level positive input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential LVNECL output signals (−2.5 V / −3.3 V). To accomplish the level translation the LVEP91 requires three power rails. The VCC pins should be connected to the positive power supply, and the VEE pin should be connected to the negative power supply. The GND pins are connected to the system ground plane. Both VEE and VCC should be bypassed to ground via 0.01 mF capacitors. Under open input conditions, the D input will be biased at VCC/2 and the D input will be pulled to GND. These conditions will force the Q outputs to a low state, and Q outputs to a high state, which will ensure stability. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. Features • Maximum Input Clock Frequency > 2.0 GHz Typical • Maximum Input Data Rate > 2.0 Gb/s Typical • 500 ps Typical Propagation Delay • Operating Range: ♦ VCC = 2.375 V to 3.8 V; VEE = −2.375 V to −3.8 V; GND = 0 V • Q Output will Default LOW with Inputs Open or at GND • These Devices are Pb-Free, Halogen Free and are RoHS Compliant MARKING DIAGRAMS* SOIC−20 WB DW SUFFIX CASE 751D−05 1 20 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb-Free Package N100 VP91 ALYWG G 1 24 QFN−24 MN SUFFIX CASE 485L−01 24 1 20 1 NB100LVEP91 AWLYYWWG www.onsemi.com (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping† MB100LVEP91DWG SOIC−20 WB (Pb-Free) 38 Units/Tube MB100LVEP91DWR2G SOIC−20 WB (Pb-Free) 1000/Tape & Reel QFN−24 (Pb-Free) MB100LVEP91MNR2G 3000/Tape & Reel QFN−24 (Pb-Free) MB100LVEP91MNG 92 Units/Tube †For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. |
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