NB4L6254

http://onsemi.com

8

Example Configurations

Figure 7. 2 x 2 Clock Switch

CLK0

CLK1

SEL0

SEL1

System A

System B

3

3

SEL0

SEL1

Switch Configuration

0

0

CLK0 Clocks System A and

System B

0

1

CLK1 Clocks System A and

System B

1

0

CLK0 Clocks System A and CLK1

Clocks System B

1

1

CLK1 Clocks System B and CLK1

Clocks System A

Figure 8. 1:6 Clock Fanout Buffer

CLK0

CLK1

SEL0

SEL1

0

0

Figure 9. Loopback Device

System−Tx

CLK0

SEL0

SEL1

QBn

CLK1

Transmitter

QAn

System−Rx

Receiver

SEL0

SEL1

Switch Configuration

0

0

System Loopback

0

1

Line Loopback

1

0

Transmit/Receive Operation

1

1

System and Line Loopback

APPLICATIONS INFORMATION

Maintaining Lowest Device Skew

The NB4L6254 guarantees low output−output bank skew

at 50 ps and a part−to−part skew of 250 ps. To ensure low

skew clock signals in the application, both outputs of any

differential output pair need to be terminated identically,

even if only one output is used. When fewer than all nine

output pairs are used, identical termination of all output pairs

within the output bank is recommended. If an entire output

bank is not used, it is recommended to leave all of these

outputs open and unterminated. This will reduce the device

power consumption while maintaining minimum output

skew.

Power Supply Bypassing

The NB4L6254 is a mixed analog/digital product. The

differential architecture of the NB4L6254 supports low

noise signal operation at high frequencies. In order to

bypassed by high−frequency ceramic capacitors connected

to GND. If the spectral frequencies of the internally

generated switching noise on the supply pins cross the series

resonant port of an individual bypass capacitor, its overall

impedance begins to look inductive and thus increases with

increasing frequency. The parallel capacitor combination

shown ensures that a low impedance path to ground exists

for frequencies well above the noise bandwidth.

NB4L6254

33 − 100 nF

0.1 nF