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NB4L339 Datasheet(PDF) 8 Page - ON Semiconductor

Part No. NB4L339
Description  2.5 V / 3.3 V Differential 2:1 Clock IN to Differential LVPECL Clock Generator
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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NB4L339 Datasheet(HTML) 8 Page - ON Semiconductor

 
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NB4L339
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8
Figure 6. Timing Diagram
MR
CLK
Q (÷1)
Q (÷2)
Q (÷4)
Q (÷8)
Figure 7. Master Reset Timing Diagram
NOTE: On the rising edge of MR, Q goes HIGH after the first rising edge of CLK, following a high−to−low clock transition.
CLK
MR
Q (÷n)
tRR
tRR
Figure 8. Output Enable Timing Diagrams
CLK
Q (÷n)
EN
Internal Clock
Disabled
Internal Clock
Enabled
The EN signal will “freeze” the internal divider flip−flops
on the first falling edge of CLK after its assertion. The
internal divider flip−flops will maintain their state during the
freeze. When EN is deasserted (LOW), and after the next
falling edge of CLK, then the internal divider flip−flops will
“unfreeze” and continue to their next state count with proper
phase relationships.


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