Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF HTML

NB4L339 Datasheet(PDF) 7 Page - ON Semiconductor

Part No. NB4L339
Description  2.5 V / 3.3 V Differential 2:1 Clock IN to Differential LVPECL Clock Generator
Download  12 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
Logo 

NB4L339 Datasheet(HTML) 7 Page - ON Semiconductor

Zoom Inzoom in Zoom Outzoom out
 7 / 12 page
background image
NB4L339
http://onsemi.com
7
Figure 4. NB4L339 vs. Agilent 8665A 622.08 MHz at 3.3 V, Room Ambient
Figure 5. Output Voltage Amplitude (VOUTPP) vs. Input Clock Frequency (fin) at
Ambient Temperature (Typical)
fout, CLOCK OUTPUT FREQUENCY (GHz)
700
600
500
400
300
200
100
0
1.2
0.1
0
1.0
800
0.2
0.3
0.4
0.5
0.6
0.7
0.8 0.9
1.1
Application Information
The NB4L339 is a high−speed, Clock multiplexer, divider
and low skew fan−out buffer featuring a 2:1 Clock
multiplexer front end and outputs a selection of four
different divide ratios;
÷1/2/4/8. One divide block has a
choice of
÷1 or ÷ 2. The outputs of all four divider blocks are
fanned−out to two pair of identical differential LVPECL
copies of the selected clock. All outputs provide standard
LVPECL voltage levels when externally terminated with a
50−ohm resistor to VTT = VCC − 2 V.
The differential Clock input buffers incorporate internal
50−
W termination resistors in a 100−W center−tapped
configuration and are accessible via a VTx pin. This feature
provides transmission line termination on−chip, at the
receiver end, eliminating external components. Inputs
CLKA/B and CLKA/B must be signal driven or auto
oscillation may result.
The NB4L339 Clock inputs can be driven by a variety of
differential signal level technologies including LVDS,
LVPECL, or CML.
The internal dividers are synchronous to each other.
Therefore, the common output edges are precisely aligned.
The Output Enable pin (EN) is synchronous so that the
internal divider flip−flops will only be enabled/disabled
when the internal clock is in the LOW state. This avoids any
chance of generating a runt pulse on the internal clock when
the device is enabled/disabled, as can happen with an
asynchronous control. The internal enable flip−flop is
clocked on the falling edge of the input clock. Therefore, all
associated specification limits are referenced to the negative
edge of the clock input.
The Master Reset (MR) is asynchronous. When MR is
forced LOW, all Q outputs go to logic LOW.


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn