NB3W800L

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7

Table 12. DIF 0.7 V AC TIMING CHARACTERISTICS (Non−Spread or −0.5% Spread Spectrum Mode)

Symbol

Parameter

CLK = 100 MHz, 133.33 MHz

Unit

Min

Max

Tstab (Note 32)

Clock Stabilization Time

1.8

ms

Laccuracy (Notes 15, 19, 27, 33)

Long Accuracy

100

ppm

Tabs (Notes 15, 16, 19)

Absolute

Min/Max

Host CLK

Period

No Spread

9.94900 for 100 MHz

10.05100 for 100 MHz

ns

7.44925 for 133 MHz

7.55075 for 133 MHz

−0.5% Spread

9.49900 for 100 MHz

10.10126 for 100 MHz

7.44925 for 133 MHz

7.58845 for 133 MHz

Slew_rate (Notes 13, 15, 19)

DIFF OUT Slew_rate

1.0

4.0

V/ns

DTrise / DTfall (Notes 15, 19, 29)

Rise and Fall Time Variation

125

ps

Rise/Fall Matching (Notes 15, 19, 30, 31)

20

%

VHigh (Notes 15, 18, 21)

Voltage High (typ

0.70 Volts)

660

850

mV

VLow (Notes 15, 18, 22)

Voltage Low (typ

0.0 Volts)

−150

150

mV

Vmax (Note 18)

Maximum Voltage

1150

mV

Vcross absolute (Notes 12, 14, 15, 18, 25)

Absolute Crossing Point Voltages

250

550

mV

Vcross relative (Notes 15, 17, 18, 25)

Relative Crossing Point Voltages

Calc

Calc

Total

D Vcross (Notes 15, 18, 26)

Total Variation of Vcross

Over All Edges

140

mV

Vovs (Notes 15, 18, 23)

Maximum Voltage (Overshoot)

Vhigh + 0.3

V

Vuds (Notes 15, 18, 24)

Maximum Voltage (Undershoot)

Vlow − 0.3

V

12. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLK#.

13. Measurment taken from differential waveform on a component test board. The slew rate is measured from −150 mV to +150 mV on the

differential waveform. Scope is set to average because the scope sample clock is making most of the dynamic wiggles along the clock edge

Only valid for Rising CLK_IN and Falling CLK_IN#. Signal must be monotonic through the Vol to Voh region for Trise and Tfall.

14. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.

15. Test configuration is; Rs = 27

W, 2 pF for 85 W transmission line.

16. The average period over any 1

ms period of time must be greater than the minimum and less than the maximum specified period.

17. Vcross(rel) Min and Max are derived using the following, Vcross(rel) Min = 0.250 + 0.5 (Vhavg − 0.700), Vcross(rel) Max = 0.550 − 0.5 (0.700

– Vhavg)

18. Measurement taken from Single Ended waveform.

19. Measurement taken from differential waveform. Bypass mode, input duty cycle = 50%.

20. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

21. VHigh is defined as the statistical average High value as obtained by using the Oscilloscope VHigh Math function.

22. VLow is defined as the statistical average Low value as obtained by using the Oscilloscope VLow Math function.

23. Overshoot is defined as the absolute value of the maximum voltage.

24. Undershoot is defined as the absolute value of the minimum voltage.

25. The crossing point must meet the absolute and relative crossing point specifications simultaneously.

26.

DVcross is defined as the total variation of all crossing voltages of Rising DIF and Falling DIF#. This is the maximum allowed variance in

Vcross for any particular system.

27. Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are 100,000,000 Hz, 133,333,333 Hz.

28. Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are 99,750,00 Hz, 133,000,000 Hz.

29. Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max

.

30. Measured with oscilloscope, averaging on, The difference between the rising edge rate (average) of DIF versus the falling edge rate

(average) of DIF#. Measured in a

±75 mV window around the crosspoint of DIF and DIF#.

31. Rise/Fall matching is derived using the following, 2*(Trise – Tfall) / (Trise + Tfall).

32. This is the time from the valid CLK_IN input clocks and the assertion of the PWRGD signal level at 1.8 V – 2.0 V to the time that stable clocks

are output from the buffer chip (PLL locked).

33. All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK410B+/CK420BQ accuracy

requirements. The NB3W800L itself does not contribute to ppm error.