NB3W800L_16 datasheet(2/17 Pages) ONSEMI

Part #	NB3W800L

Description	Differential 1:8 HCSLCompatible Push-Pull Clock

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NB3W800L

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Figure 1. Simplified Block Diagram

FB_OUT

DIF[7:0]

Control

Logic

CLK_IN

SSC Compatible

PLL

8

SDA

SCL

MUX

100M_133M#

PWRGD/PWRDN#

HBW_BYP_LBW#

OE[7:0]#

CLK_IN#

FB_OUT#

DIF[7:0]#

Table 1. OE AND POWER PIN TABLE

Inputs

OE# Hardware Pins & Control Register Bits

Outputs

PLL State

PWRGD/

PWRDN#

CLK_IN/

CLK_IN#

SMBUS

Enable Bit

OE# Pin

DIF/DIF# [7:

0]

FB_OUT/

FB_OUT#

0

X

Hi−Z

OFF

1

Running

0

X

Hi−Z

Running

ON

1

0

Running

ON

1

Hi−Z

Running

ON

Table 2. FUNCTIONALITY AT POWER−UP (PLL MODE)

100M_133M#

CLK_IN MHz

DIF(7:0)

1

100.00

CLK_IN

0

133.33

CLK_IN

Table 3. POWER CONNECTIONS

Pin Number

Description

VDD

GND

44

49

Analog PLL

3

2

Analog Input

10, 15, 19, 27, 34, 38, 42

49

DIF clocks

Table 4. SMBus ADDRESS

Address

+ Read/Write bit

D8

R

Table 5. PLL OPERATING MODE READBACK TABLE

HBW_BYP_LBW#

Byte0, bit 7

Byte 0, bit 6

Low (Low BW)

0

Mid (Bypass)

0

1

High (High BW)

1

Table 6. TRI−LEVEL INPUT THRESHOLDS

Level

Voltage

Low

<0.8 V

Mid

1.2<Vin<1.8 V

High

Vin > 2.2 V

Table 7. PLL OPERATING MODE

HBW_BYP_LBW#

Mode

Low

PLL Lo BW

Mid

Bypass

High

PLL Hi BW

NOTE:

PLL is OFF in Bypass Mode

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