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NB3V1102CDTR2G Datasheet(PDF) 1 Page - ON Semiconductor

Part # NB3V1102CDTR2G
Description  3.3V/2.5V/1.8V LVCMOS Low Skew Fanout Buffer Family
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NB3V1102CDTR2G Datasheet(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2016
March, 2016 − Rev. 2
1
Publication Order Number:
NB3V1102C/D
NB3V110xC Series
3.3V/2.5V/1.8V LVCMOS
Low Skew Fanout Buffer
Family
Description
The NB3V110xC are a modular, high−performance, low−skew,
general purpose LVCMOS clock buffer family. The family of devices
is designed with a modular approach. Four different fan−out
variations, 1:2, 1:3, 1:4, 1:6 and 1:8, are available. All of the devices
are pin compatible to each other for easy handling. All family
members share the same high performing characteristics like low
additive jitter, low skew, and wide operating temperature range. The
NB3V110xC supports an asynchronous output enable control (OE)
which switches the outputs into a low state when OE is low. The
NB3V110xC devices operate in a 3.3 V, 2.5 V and 1.8 V environment
and are characterized for operation from −40
°C to 105°C.
Features
Operating Temperature Range: –40°C to 105°C
High−Performance 1:2, 1:3, 1:4, 1:6, 1:8 LVCMOS Clock Buffer
Available in 8−, 14−, 16−Pin TSSOP and WDFN8 Packages
Very Low Output−to−Output Skew < 50 ps
Very Low Additive Jitter < 200 fs
Supply Voltage: 3.3 V, 2.5 V or 1.8 V
fmax = 250 MHz for 3.3 V; fmax = 180 MHz for 2.5 V;
fmax = 133 MHz for 1.8 V
These Devices are Pb−Free and are RoHS Compliant
BLOCK DIAGRAM
Q0
Q1
Q2
Q3
Qn
CLKIN
LV
CMOS
OE
LV
CMOS
LV
CMOS
LV
CMOS
LV
CMOS
LV
CMOS
S
S
S
This document contains information on some products that are still under development.
ON Semiconductor reserves the right to change or discontinue these products without
notice.
www.onsemi.com
See detailed ordering, marking and shipping information on
page 8 of this data sheet.
ORDERING INFORMATION
MARKING DIAGRAMS
A
= Assembly Location
M
= Date Code
L
= Wafer Lot
Y
= Year
W, WW
= Work Week
G
= Pb−Free Package
TSSOP−14
TSSOP−8
1106
V
ALYW
G
G
1
14
(Note: Microdot may be in either location)
TSSOP−16
DT SUFFIX
CASE 948F
TSSOP−8
DT SUFFIX
CASE 948S
10x
YWW
A
G
1
8
WDFN8, 2x2
MT SUFFIX
CASE 511AQ
0X M
G
G
1
WDFN8
TSSOP−14
DT SUFFIX
CASE 948G
1108
V
ALYW
G
G
1
16
TSSOP−16


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