NB3N5573

www.onsemi.com

4

Symbol

Characteristic

Min

Typ

Max

Unit

Clock/Crystal Input Frequency

25

MHz

Output Clock Frequency

25

200

MHz

Phase−Noise Performance

dBc/Hz

@ 100 Hz offset from carrier

−103/−109

@ 1 kHz offset from carrier

−118/−127.8

@ 10 kHz offset from carrier

−122/−136.2

@ 100 kHz offset from carrier

−130/−138.8

@ 1 MHz offset from carrier

−132/−138.2

@ 10 MHz offset from carrier

−149/−164

Period Jitter Peak−to−Peak (Note 6)

10

20

ps

Period Jitter RMS (Note 6)

1.5

3

Cycle−Cycle RMS Jitter (Note 7)

2

5

Cycle−to−Cycle Peak to Peak Jitter (Note 7)

20

35

ps

Additive Phase RMS Jitter, Integration Range 12 kHz to 20 MHz

0.4

ps

OE

Output Enable/Disable Time

10

ms

Output Clock Duty Cycle (Measured at cross point)

45

50

55

%

Output Risetime (Measured from 175 mV to 525 mV, Figure 5)

175

340

700

ps

Output Falltime (Measured from 525 mV to 175 mV, Figure 5)

175

340

700

ps

Output Risetime Variation (Single−Ended)

125

ps

Output Falltime Variation (Single−Ended)

125

ps

Stabilization

Time

3.0

ms

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm.

of 2 pF and current biasing resistor set at 475

W. See Figure 3.

6. Sampled with 10000 cycles.

7. Sampled with 1000 cycles.