NB3N51032

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2

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

S0

S1

SS0

X1/CLK

X2

OE

GNDXD

SS1

VDDXD

CLK0

GNDODA

VDDODA

IREF

CLK0

Figure 2. Pin Configuration (Top View)

CLK1

CLK1

Table 1. PIN DESCRIPTION

Pin

Symbol

I/O

Description

1

S0

Input

LVTTL/LVCMOS frequency select input 0. Internal pullup resistor to VDDXD. See output

select table 2 for details.

2

S1

Input

LVTTL/LVCMOS frequency select input 1. Internal pullup resistor to VDDXD. See output

select Table 2 for details.

3

SS0

Input

LVTTL/LVCMOS Spread select input 0. Internal pullup resistor to VDDXD. See Spread se-

lection Table 3 for details.

4

X1/CLK

Input

Crystal or Clock input. Connect to 25 MHz crystal source or single−ended clock.

5

X2

Input

Crystal input. Connect to a 25 MHz crystal or leave unconnected for clock input.

6

OE

Input

Output enable tri−states output when connected to GND. Internal pullup resistor to VDDXD.

7

GNDXD

Power Supply

Ground 0 V. This pin provides GND return path for the device.

8

SS1

Input

LVTTL/LVCMOS Spread select input 1. Internal pullup resistor to VDDXD. See Spread se-

lection Table 3 for details.

9

IREF

Output

Output current reference pin. Precision resistor (typ. 475

W) is connected to set the output

current.

10

CLK1

HCSL or

LVDS Output

Inverted clock output. (For LVDS levels see Figure 10)

11

CLK1

HCSL or

LVDS Output

Noninverted clock output. (For LVDS levels see Figure 10)

12

VDDODA

Power Supply

Positive supply voltage pin connected to +3.3 V supply voltage.

13

GNDODA

Power Supply

Ground 0 V. These pins provide GND return path for the devices.

14

CLK0

HCSL or

LVDS Output

Inverted clock output. (For LVDS levels see Figure 10)

15

CLK0

HCSL or

LVDS Output

Noninverted clock output. (For LVDS levels see Figure 10)

16

VDDXD

Power Supply

Positive supply voltage pin connected to +3.3 V supply voltage.