NB3N1200K, NB3W1200L

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10

Table 6. LOW BAND PHASE JITTER − PLL MODE

Group

Parameter

Min

Typ

Max

Units

DIF

(Notes 14, 16, 17)

Output PCIe Gen1

13

86

ps

(p−p)

DIF

(Notes 14, 15, 17, 19)

Output PCIe Gen2 Low Band, 10 kHz < f < 1.5 MHz

0.1

3.0

ps

RMS

DIF

(Notes 14, 15, 17, 19)

Output PCIe Gen2 High Band, 1.5 MHz < f < 50 MHz

0.8

3.1

ps

RMS

HIGH BAND

, 1.5 MHz < F < Nyquist

DIF

(Notes 14, 15, 17, 19)

Output phase jitter impact – PCIe* Gen3

(including PLL BW 2 – 4 MHz, CDR = 10 MHz)

0.18

1.0

ps

RMS

DIF

(Notes 14, 18, 20)

Output Intel QPI & Intel SMI REFCLK accumulated jitter

(4.8 Gb/s or 6.4 Gb/s, 100 MHz or 133 MHz, 12 UI)

0.14

0.5

ps

RMS

DIF

(Notes 14, 18)

Output Intel QPI & Intel SMI REFCLK accumulated jitter

(8 Gb/s, 100 MHz, 12 UI)

0.07

0.3

ps

RMS

DIF

(Notes 14, 18)

Output Intel QPI & Intel SMI REFCLK accumulated jitter

(9.6 Gb/s, 100 MHz, 12 UI)

0.06

0.2

ps

RMS

Table 7. ADDITIVE PHASE JITTER − BYPASS MODE

Group

Parameter

Min

Typ

Max

Units

DIF

(Notes 14, 16, 17)

Output PCIe Gen1

0.04

10

ps

(p−p)

DIF

(Notes 14, 15, 17, 19)

Output PCIe Gen2 Low Band, 10 kHz < f < 1.5 MHz

0.001

0.3

ps

RMS

DIF

(Notes 14, 15, 17, 19)

Output PCIe Gen2 High Band, 1.5 MHz < f < 50 MHz

0.002

0.7

ps

RMS

DIF

(Notes 14, 15, 17, 19)

Output phase jitter impact – PCIe* Gen3

0.001

0.3

ps

RMS

DIF

(Notes 14, 18, 20)

Output Intel QPI & Intel SMI REFCLK accumulated jitter

(4.8 Gb/s or 6.4 Gb/s, 100 MHz or 133 MHz, 12 UI)

0.001

0.3

ps

RMS

DIF

(Notes 14, 18)

Output Intel QPI & Intel SMI REFCLK accumulated jitter

(8 Gb/s, 100 MHz, 12 UI)

0.001

0.1

ps

RMS

DIF

(Notes 14, 18)

Output Intel QPI & Intel SMI REFCLK accumulated jitter

(9.6 Gb/s, 100 MHz, 12 UI)

0.001

0.1

ps

RMS

14. Post processed evaluation through Intel supplied Matlab scripts. Tested with NB3N1200K/NB3W1200L driven by a CK420BQ or equivalent.

15. PCIe Gen3 filter characteristics are subject to final ratification by PCISIG. Please check the PCI SIG for the latest specification.

16. These jitter numbers are defined for a BER of 1E−12. Measured numbers at a smaller sample size have to be extrapolated to this BER target.

17.

⎛ = 0.54 is implying a jitter peaking of 3 dB.

18. Measuring on 100 MHz output using Intel supplied clock template jitter tool.

19. Measuring on 100 MHz PCIe SRC output using Intel supplied clock jitter tool.

20. Measuring on 100 MHz, 133 MHz output using Intel supplied clock jitter tool.

Table 8. PLL BANDWIDTH AND PEAKING

Group

Parameter

Min

Typ

Max

Units

DIF (Note 21)

PLL Jitter Peaking (HBW_BYPASS_LBW# = 0)

−

0.7

2

.0

dB

DIF (Note 21)

PLL Jitter Peaking (HBW_BYPASS_LBW# = 1)

−

0.4

2

.5

dB

DIF (Note 22)

PLL Bandwidth (HBW_BYPASS_LBW# = 1)

2.0

2.7

4.0

MHz

DIF (Note 22)

PLL Bandwidth (HBW_BYPASS_LBW# = 0)

0.7

0.9

1

.4

MHz

21. Measured as maximum pass band gain

. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.

22. Measured at 3 db down or half power point.