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K6F1616T6B Datasheet(PDF) 8 Page - Samsung semiconductor

Part No. K6F1616T6B
Description  1M x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
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Manufacturer  SAMSUNG [Samsung semiconductor]
Direct Link  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

K6F1616T6B Datasheet(HTML) 8 Page - Samsung semiconductor

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K6F1616T6B Family
Revision 1.0
August 2003
8
CMOS SRAM
DATA RETENTION WAVEFORM
VCC
2.7V
2.2V
VDR
GND
Data Retention Mode
tSDR
tRDR
CS2 controlled
VCC
2.7V
0.4V
VDR
CS2
GND
Data Retention Mode
tSDR
tRDR
CS2
≤0.2V
CS1 controlled
CS1
CS1
≥VCC - 0.2V
Address
Data Valid
UB, LB
WE
Data in
Data out
High-Z
High-Z
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran-
sition when CS1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS1 going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1 or WE going high.
tWC
tCW(2)
tBW
tWP(1)
tDH
tDW
tWR(4)
tAW
tAS(3)
CS1
CS2


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