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TS80C51RA2-LCBB Datasheet(PDF) 17 Page - ATMEL Corporation |
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TS80C51RA2-LCBB Datasheet(HTML) 17 Page - ATMEL Corporation |
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17 / 74 page  Rev. C - 06 March, 2001 17 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Figure 4. Internal and External Data Memory Address Table 5. Auxiliary Register AUXR AUXR Address 08EH - - - - - - EXTRA M AO Reset value X X X X X X 0 0 Symbol Function - Not implemented, reserved for future use.a a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. AO Disable/Enable ALE AO Operating Mode 0 ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used) 1 ALE is active only during a MOVX or MOVC instruction EXTRAM Internal/External RAM (00H-FFH) access using MOVX @ Ri/ @ DPTR EXTRAM Operating Mode 0 Internal XRAM access using MOVX @ Ri/ @ DPTR 1 External data memory access XRAM 256 bytes Upper 128 bytes Internal Ram Lower 128 bytes Internal Ram Special Function Register 80 80 00 FF(RA, RB, RC)/2FF (RD) FF 00 FF External Data Memory 0000 0100 (RA, RB, RC) or 0300 (RD) FFFF indirect accesses direct accesses direct or indirect accesses |
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