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IDT72V3622 Datasheet(PDF) 1 Page - Integrated Device Technology

Part No. IDT72V3622
Description  3.3 VOLT CMOS SyncBiFIFO 256 x 36 x 2 512 x 36 x 2 1,024 x 36 x 2
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT72V3622 Datasheet(HTML) 1 Page - Integrated Device Technology

 
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2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4660/4
DECEMBER 2001
3.3 VOLT CMOS SyncBiFIFOTM
256 x 36 x 2
512 x 36 x 2
1,024 x 36 x 2
IDT72V3622
IDT72V3632
IDT72V3642
IDT, the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
.EATURES:
••••• Memory storage capacity:
IDT72V3622
256 x 36 x 2
IDT72V3632
512 x 36 x 2
IDT72V3642
1,024 x 36 x 2
••••• Supports clock frequencies up to 100 MHz
••••• Fast access times of 6.5ns
••••• Free-running CLKA and CLKB may be asynchronous or coincident
(simultaneous reading and writing of data on a single clock edge
is permitted)
••••• Two independent clocked FIFOs buffering data in opposite direc-
tions
••••• Mailbox bypass register for each FIFO
••••• Programmable Almost-Full and Almost-Empty flags
••••• Microprocessor Interface Control Logic
••••• FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA
••••• FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB
••••• Select IDT Standard timing (using EFA, EFB, FFA and FFB flags
functions) or First Word Fall Through timing (using ORA, ORB, IRA
and IRB flag functions)
••••• Available in 132-pin Plastic Quad Flatpack (PQFP) or space-saving
120-pin Thin Quad Flatpack (TQFP)
••••• Functionally compatible to the 5V operating IDT723622/723632/
723642
••••• Industrial temperature range (–40οοοοοC to +85οοοοοC) is available
DESCRIPTION:
TheIDT72V3622/72V3632/72V3642arefunctionallycompatibleversions
of the IDT723622/723632/723642, designed to run off a 3.3V supply for
exceptionally low-power consumption. These devices are monolithic, high-
speed, low-power, CMOS Bidirectional SyncFIFO (clocked) memories which
support clock frequencies up to 100MHz and have read access times as fast
as 6.5ns. Two independent 256/512/1,024 x 36 dual-port SRAM FIFOs on
board each chip buffer data in opposite directions. Communication between
.UNCTIONAL BLOCK DIAGRAM
Mail 1
Register
Programmable Flag
Offset Registers
RAM
ARRAY
256 x 36
512 x 36
1,024 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
RAM
ARRAY
256 x 36
512 x 36
1,024 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
CLKA
CSA
W/
RA
ENA
MBA
Port-A
Control
Logic
FIFO1,
Mail1
Reset
Logic
RST1
Mail 2
Register
MBF2
CLKB
CSB
W/RB
ENB
MBB
Port-B
Control
Logic
FIFO2,
Mail2
Reset
Logic
RST2
MBF1
FIFO 1
FIFO 2
10
EFB/ORB
AEB
36
36
FFB/IRB
AFB
B0 - B35
FFA/IRA
AFA
FS0
FS1
A0 - A35
EFA/ORA
AEA
4660 drw 01
36
36
Timing
Mode
FWFT


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