IDT72V3622 datasheet(23/29 Pages) IDT

Part #	IDT72V3622

Description	3.3 VOLT CMOS SyncBiFIFO 256 x 36 x 2 512 x 36 x 2 1,024 x 36 x 2

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

NOTE:

1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising

CLKB edge is less than tSKEW1, then IRB may transition HIGH one CLKB cycle later than shown.

Figure 14. IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)

CSA

ORA

W/

RA

MBA

ENA

A0- A35

CLKA

IRB

CLKB

CSB

4660 drw 16

W/RB

B0 - B35

MBB

ENB

12

tCLK

tCLKH

tCLKL

tENS2

tENH

tA

tSKEW1

tCLK

tCLKH

tCLKL

tWEF

tENS2

tENH

tDS

tDH

To FIFO2

Previous Word in FIFO2 Output Register

Next Word From FIFO2

FIFO2 FULL

LOW

HIGH

LOW

(1)

Write

tWEF

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IDT72V3622 Datasheet(PDF) 23 Page - Integrated Device Technology

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