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IDT72V3622 Datasheet(PDF) 2 Page - Integrated Device Technology

Part No. IDT72V3622
Description  3.3 VOLT CMOS SyncBiFIFO 256 x 36 x 2 512 x 36 x 2 1,024 x 36 x 2
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT72V3622 Datasheet(HTML) 2 Page - Integrated Device Technology

 
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IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
DESCRIPTION (CONTINUED)
NOTES:
1. NC – no internal connection
2. Uses Yamaichi socket IC51-1324-828
PQFP (PQ132-1, order code: PQF)
TOP VIEW
NC
NC
A35
A34
A33
A32
VCC
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
FWFT
A22
VCC
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
VCC
A12
NC
NC
B35
B34
B33
B32
GND
B31
B30
B29
B28
B27
B26
VCC
B25
B24
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
VCC
B15
B14
B13
B12
GND
NC
NC
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4660 drw 02
*
eachportmaybypasstheFIFOsviatwo36-bitmailboxregisters.Eachmailbox
register has a flag to signal when new mail has been stored.
These devices are a synchronous (clocked) FIFO, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
These devices have two modes of operation: In the IDT Standard mode,
the first word written to an empty FIFO is deposited into the memory array. A
read operation is required to access that word (along with all other words
residing in memory). In the First Word Fall Through mode (FWFT), the first
long-word (36-bit wide) written to an empty FIFO appears automatically on the
outputs, no read operation required (Nevertheless, accessing subsequent
words does necessitate a formal read request). The state of the
FWFT pin
during FIFO operation determines the mode in use.
Each FIFO has a combined Empty/Output Ready Flag (
EFA/ORA and
EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFB/
IRB). The
EF and FF functions are selected in the IDT Standard mode. EF
indicates whether or not the FIFO memory is empty.
FF shows whether the
memory is full or not. The IR and OR functions are selected in the First Word
FallThroughmode.IRindicateswhetherornottheFIFOhasavailablememory
locations. OR shows whether the FIFO has data available for reading or not.
It marks the presence of valid data on the outputs.
*Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
PIN CON.IGURATION


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