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SIC645 Datasheet(PDF) 12 Page - Vishay Siliconix

Part No. SIC645
Description  60 A VRPower Smart Power Stage (SPS) Module with Integrated High-Accuracy Current and Temperature Monitors
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Maker  VISHAY [Vishay Siliconix]
Homepage  http://www.vishay.com
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SIC645 Datasheet(HTML) 12 Page - Vishay Siliconix

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SiC645
www.vishay.com
Vishay Siliconix
S16-2233-Rev. B, 31-Oct-16
12
Document Number: 65424
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PCB LAYOUT CONSIDERATIONS
Proper PCB layout will reduce noise coupling to other
circuits, improve thermal performance, and maximize the
efficiency. The following is meant to lead to an optimized
layout:
• Place multiple 10 μF or greater ceramic capacitors directly
at device between VIN and PGND as indicated in Fig. 16
This is the most critical decoupling and reduced parasitic
inductance in the power switching loop. This will reduce
overall electrical stress on the device as well as reduce
coupling to other circuits. Best practice is to place the
decoupling capacitors on the same PCB side as the
device.
For a design with tight space requirements, these
decoupling capacitors can be placed under the device,
i.e., bottom layer, as shown in Fig. 18
• Connect GND to the system GND plane with a large via
array as close to the GND pins as design rules allow. This
improves thermal and electrical performance.
•Place
PVCC,
VCC
and
BOOT-PHASE
decoupling
capacitors at the IC pins as shown in Fig. 16.
• Note that the SW plane connecting the SiC645 and
inductor must carry full load current and will create
resistive loss if not sized properly. However, it is also a
very noisy node that should not be oversized or routed
close to any sensitive signals. Best practice is to place the
inductor as close to the device as possible and thus
minimizing the required area for the SW connection. If one
must choose a long route of either the VOUT side of the
inductor or the SW side, choose the quiet VOUT side. Best
practice is to locate the SiC645 as close to the final load
as possible and thus avoid noisy or lossy routes to the
load.
• The IMON and IREF network and their vias should not sit
on the top of the VIN plane, a keep out area is
recommended, as shown in Fig. 18.
• The PCB is the best thermal heatsink material than any top
side cooling materials. The PCB always has enough vias
to connect VIN and GND planes. Insufficient vias will yield
lower efficiency and very poor thermal performance.
Fig. 17 and Fig. 18 show a multiphase PCB layout example.
TABLE 2 - FAULT REPORTING SUMMARY
FAULT EVENT
IMON
TMON
FAULT#
RESPONSE
OC
High
n/a
Low
GH gated off. The controller should acknowledge and
force its PWM to tri-state to keep both HFET and LFET
off. The fault is cleared
 1 μs after PWM enters
tri-state, otherwise, it stays asserted. (if system OVP
occurs, the controller may sen PWM to turn on LEFT)
Shorted HFET
IMON latched high
n/a
FAULT# latched low
GH gated off, until fault latch is cleared by VCC POR. GL
follows PWM.
OT
n/a
High
Low
GH and GL follow PWM.
VCC UVLO
IMON - REFIN = 0 V
TMON not valid
Low
Switching stops while in UVLO. Once above VCC POR
after 125 μs: GH and GL follow PWM; the FAULT# is
released; TMON is valid; IMON - REFIN is valid after GL
first goes low.
VIN UVLO
OC not valid
n/a
Low
GH and GL follow PWM.


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