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SIC645 Datasheet(PDF) 11 Page - Vishay Siliconix
VISHAY [Vishay Siliconix]
SIC645 Datasheet(HTML) 11 Page - Vishay Siliconix
/ 18 page
S16-2233-Rev. B, 31-Oct-16
Document Number: 65424
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
The HFET current is not monitored in the same way, so no
valid measured current is available while PWM is high (and
the short delays before and after). During this time, the
IMON will output the last valid LFET current before the
sampling stopped. On start-up after POR, the IMON will
output zero (relative to REF
, which represents zero current)
until the switching begins, and then the current can be
The high-side FET current is separately monitored for OC
conditions; see the “over-current protection” section.
Fig. 14 shows the timing diagram of an over-current fault.
There is a comparator monitoring the HFET current while it
is on (GH high; also requires V
POR above its trip point).
user-programmable), then an OC fault is detected. The GH
will be forced low, even if PWM is still high; this effectively
shortens the PWM (and GH) pulse width, to limit the current.
The IMON pin is pulled up to REF
+1.2 V, which will be
detected by the controller as an over-current fault. The
controller is then expected to force PWM to tri-state (which
gates off both FETs) or low state (turns on LFET), either of
acknowledged. This starts a ~ 1 μs fault clear delay. The
IMON flag is released after the delay. The driver will then
respond to PWM inputs normally.
Note that if the controller does NOT acknowledge, the IMON
flag will stay high indefinitely, which will also hold GH low.
If OC is detected, the FAULT# pin is also pulled low; the
timing on the FAULT# pin will follow that of the IMON pin.
Fig. 14 - Over-current Fault Timing Diagram
Shorted HFET Protection
In the case of a shorted HFET, the SW node will have
excessive positive voltage present even when the LFET is
turned on. The SiC645 monitors the SW node during periods
when the LFET is on (GL is high), and should that voltage
exceed 100 mV (typical), the HFET short fault is declared.
The SiC645 will pull the IMON pin high, and the FAULT# will
be pulled low. But the fault will be latched; V
needed to reset it. GH will be gated low (ignore PWM = high),
but the SiC645 will still respond to PWM tri-state and logic
The SiC645 monitors its internal temperature and provides
a signal proportional to that temperature on the TMON pin.
TMON has a voltage of 600 mV at 0 °C and reflects
temperature at 8 mV/°C. The TMON output is valid 125 μs
Fig. 15 - Over-Temperature Fault
Fig. 15 shows a simplified functional representation. The top
section includes the sensor and the output buffer. The
bottom section includes the protection sensing, that will pull
the output high. The TMON pin is configured internally such
that a user can tie multiple pins together externally and the
resulting TMON bus will assume the voltage of the highest
contributor (representing the highest temperature).
If the internal temperature exceeds the over-temperature
trip point (+140 °C typical), the TMON pin is pulled high (to
~2.5 V), and the FAULT# pin is pulled low. No other action is
taken on-chip. Both the TMON and FAULT# pins will remain
in the fault mode, until the junction temperature drops below
+125 °C typical; at that point, the TMON and FAULT# pins
resume normal operation; the DMP can detect that the fault
condition has gone away, and decide what to do next.
Over-current and shorted HFET detections will pull the
IMON pin to a high (fault) level, such that the DMP should
Over-temperature detection will pull the TMON pin to a high
(fault) level, such that the PWM controller should quickly
recognize it as out of the normal range.
All of the above faults, plus the V
conditions, will also pull down the FAULT# pin. This can be
used by the controller (or system) as fault detection, and can
also be used to disable the controller, through its enable pin.
The fault reporting and respective SPS response are
summarized in Table 2.
FollowPWM low to
support OV following OC
No GH allowed
DMP enters PWM mid-state
or low to acknowledge fault
600 mV + 8 mV/°C x temperature
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