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SIC645 Datasheet(PDF) 10 Page - Vishay Siliconix

Part No. SIC645
Description  60 A VRPower Smart Power Stage (SPS) Module with Integrated High-Accuracy Current and Temperature Monitors
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Maker  VISHAY [Vishay Siliconix]
Homepage  http://www.vishay.com
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SIC645 Datasheet(HTML) 10 Page - Vishay Siliconix

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SiC645
www.vishay.com
Vishay Siliconix
S16-2233-Rev. B, 31-Oct-16
10
Document Number: 65424
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
DETAILED OPERATIONAL DESCRIPTION
The SiC645 is an optimized driver and power stage solution
for high density synchronous DC/DC power conversion. It
includes high performance GH and GL drivers, a NFET
controlled to function as a bootstrap diode, and MOSFET
pair optimized for high switching frequency buck voltage
regulators. It also includes advanced power management
features.
1. Accurate current and thermal reporting outputs
2. Fault protections of HFET over-current, HFET short,
over-temperature, VCC UVLO, and VIN UVLO
Power-On Reset (POR)
During initial start-up, the VCC voltage rise is monitored.
Once the rising VCC voltage exceeds 3.86 V (typical) for
125 μs, then normal operation of the driver is enabled. The
PWM signals are passed through to the gate drivers, the
TMON output is valid, and the IMON output starts at zero,
and becomes valid on the first GL signal. If VCC drops below
the falling threshold of 3.58 V (typical), operation of the
driver is disabled. The PVCC voltage is not monitored as it
should to be from the same supply as VCC.
VIN POR is also monitored. When both VCC and VIN reach
above their POR trip points, it enables HFET over-current
protection.
Both VCC and VIN POR are gated to the FAULT# pin, which
goes high once both VCC and VIN are above their POR levels
and no other faults occur.
Shoot-Through Protection
Prior to POR, the undervoltage protection function is
activated and both GH and GL are held active low (HFET
and LFET off). After POR (the rising thresholds; see electrical
specifications), and 125 μs delay, the PWM and LGCTRL
signals are used to control both high-side and low-side
MOSFETs, as shown in Table 1.
SiC645’s dead time control is optimized for high efficiency
and guarantees that simultaneous conduction of both FETs
cannot occur.
Should the driver have no bias voltage applied (either VCC or
PVCC missing) and be unable to actively hold the MOSFETs
off, an integrated 20 k
 resistor from the upper MOSFET
gate to source will aid in keeping the HFET device in its off
state. This can be especially critical in applications where
the input voltage rises prior to the SiC645 VCC and PVCC
supplies.
Tri-State PWM Input
The SiC645A supports a 3.3 V PWM tri-level input,
compatible with Vishay’s digital multiphase controllers as
well as other control IC’s utilizing 3.3 V PWM logic. Use the
SiC645 for 5 V PWM logic. Should the pin be pulled into and
remain in the tri-state window for a set hold off time
(
 25 ns), the driver will force both MOSFETs to their off
states. When the PWM signal moves outside the shutdown
window, the driver immediately resumes driving the
MOSFETs according to the PWM commands.
This feature is utilized by Vishay PWM controllers as a
method of forcing both MOSFETs off. Should the PWM
input be left floating, the pin will be pulled into the tri-state
window internally and thus force both MOSFETs to a safe off
state.
Although the PWM input can sustain a voltage as high as
VCC, the SiC645 is not compatible with a controller that
actively drives its mid-level in tri-state higher than 1.7 V.
Bootstrap Function
The SiC645 features an internal NFET that is controlled to
function as a bootstrap diode. A high quality ceramic
capacitor should be placed in close proximity across the
BOOT and PHASE pins. The bootstrap capacitor can range
between 0.1 μF to 0.22 μF (0402 to 0603 and X5R to X7R)
for normal buck switching applications.
Current Monitoring
LFET current is monitored and a signal proportional to that
current is output on the IMON pin (relative to the REFIN pin).
The IMON and REFIN pins should be connected to the
appropriate current sense input pin of the controller. This
method does not require external RSENSE or DCR sensing of
inductor current.
Fig. 13 depicts the low-side current sense concept and
demonstrates how the accuracy will be defined. After the
falling edge of PWM, there are two delays; one that
represents the expected propagation delay from PWM to
GH/SW, and a second blanking delay to allow time for the
transition to settle; typical total time is ~ 350 ns. The IMON
output approximates the actual IL waveform shown within
the tolerance band.
Fig. 13 - LFET Current Sample Diagram
TABLE 1 -
GH AND GL OPERATION TRUTH TABLE
PWM
LGCTRL
GH
GL
HFET, LFET COMMENT
Tri-state
X
0
0
Both off
-
01
0
1
LFET on
Normal
1
1
1
0
HFET on
Normal
0
0
0
0
LFET off
GL low
1
0
1
0
HFET on
Normal
On dly
Off dly
SW
GL
GH
PWM
I
L x IMON
Gain
Tolerance
Band
IMON


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