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SIC645 Datasheet(PDF) 5 Page - Vishay Siliconix

Part No. SIC645
Description  60 A VRPower Smart Power Stage (SPS) Module with Integrated High-Accuracy Current and Temperature Monitors
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Maker  VISHAY [Vishay Siliconix]
Homepage  http://www.vishay.com
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SIC645 Datasheet(HTML) 5 Page - Vishay Siliconix

 
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SiC645
www.vishay.com
Vishay Siliconix
S16-2233-Rev. B, 31-Oct-16
5
Document Number: 65424
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PINOUT CONFIGURATION
Fig. 5 - SiC645 Pinout Configuration
PIN CONFIGURATION
PIN NUMBER
NAME
FUNCTION
1
LGCTRL
Lower gate control signal input. LO = GL LO (LFET off). HI = normal operation (GL and GH strictly obey
PWM). This pin should be driven with a logic signal, or externally tied high if not required; it should not
be left floating.
2VCC
+5 V logic bias supply. Place a high quality low ESR ceramic capacitor (~1 μF/X7R) in close proximity
from this pin to GND.
3PVCC
+5 V gate drive bias supply. Place a high quality low ESR ceramic capacitor (~1 μF/X7R) in close
proximity from this pin to GND.
4, 6, 7, 8, 17, 18,
19, 20, 29, 33, 35
GND
GND pins are internally connected. Pins 4 and 29 should be connected directly to the nearby GND
paddles on package bottom. Fig. 15 shows GND paddles should be connected to the system GND
plane with as many vias as possible to maximize thermal and electrical performance.
5
NC
No connect (This is a low-side gate driver output (GL), optional to monitor for system debugging).
9, 10, 11, 12,
13, 14, 15, 16
SW
Switching junction node between HFET source and LFET drain. Connect directly to output inductor.
21, 22, 23, 27,
34
VIN
Input of power stage (to drain of HFET). Place at least 2 ceramic capacitors (10 μF or higher, X5R or
X7R) in close proximity across VIN and GND. Pin 27 should not be used for decoupling. For optimal
performance, place as many vias as possible in the bottom side VIN paddle.
24
PHASE
Return of boot capacitor. Internally connected to SW node so no external routing required for SW
connection.
25
BOOT
Floating bootstrap supply pin for the upper gate drive. Place a high quality low ESR ceramic capacitor
(0.1 μF/X7R to 0.22 μF/X7R)i n close proximity across BOOT and PHASE pins.
26
FAULT#
Open drain output pin. Any fault (over-current, over-temperature, shorted HFET, or POR / UVLO) will
pull this pin to ground. This pin may be connected to the controller enable pin or used to signal a fault
at the system level.
28
PWM
PWM input of gate driver, compatible with 3.3 V and 5 V tri-state PWM signal.
30
REFIN
Input for external reference voltage for IMON signal. This voltage should be between 0.8 V and 1.6 V.
Connect REFIN to the appropriate current sense input of the controller. Place a high quality low ESR
ceramic capacitor (~ 0.1 μF) in close proximity from this pin to GND.
31
IMON
Current monitor output, referenced to REFIN. IMON will be pulled high (to REFIN +1.2 V) to indicate an
HFET shorted or over-current fault. Connect the IMON output to the appropriate current sense input of
the controller. No more than 56 pF capacitance can be directly connected across IMON and REFIN pins.
With a 100
 series resistor, up to 470 pF may be used.
32
TMON
Temperature monitor output. For multiphase, the TMON pins can be connected together as a common
bus; the highest voltage (representing the highest temperature) will be sent to the PWM controller.
TMON will be pulled high (to 2.5 V) to indicate an over-temperature fault. No more than 250 pF total
capacitance can be directly connected across TMON and GND pins; with a series resistor, a higher
capacitance load is allowed, such as 1 k
 for 100 nF load.
1
4
2
3
5
8
6
7
17
18
19
20
21
22
23
32
31
30
29
28
27
26
25
24
910
11
12
13
14
15
16
LGCTRL
V
CC
PV
CC
GND
GL
GND
GND
GND
GND
GND
GND
GND
V
IN
V
IN
V
IN
V
IN
GND
GND
33
34
35


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