TMS626812 datasheet(35/40 Pages) TI

Part #	TMS626812

Description	1048576 BY 8-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

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35 / 40 page

See Note B

CLK

DCAB

ab

c

d

DQ

DQM

RAS

CAS

W

A10

A11

A0 – A9

CS

CKE

MRS

WRT-P B

ACTV B

R0

See Note B

C0

R0

BURST

TYPE

BANK

ROW

BURST CYCLE†

(D/Q)

(B / T )

ADDR

a

bcd

D

B

R0

C0

C0+1

C0+2

C0+3

† Column-address sequence depends on programmed burst type and starting column address C0 (see Table 5).

NOTES: A. This example illustrates minimum tRP, tRSA, and tRCD for the ’626812-12 at 83 MHz.

B. Refer to Figure 1

Figure 30. Set Mode Register (deactivate all, set mode register, write burst with automatic deactivate)

(burst length = 4)

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