NB3L204K

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3

Table 1. PIN DESCRIPTION

Pin Number

Pin Name

I/O

Description

1

VDD_O

Power

Power supply for outputs

2

OE3#

I

, SE

LVTTL / LVCMOS active low input for enabling output DIF_3/3#. 0 enables outputs, 1

disables outputs. Internal pull down.

3

CLK_IN

I, DIF

Differential True input

4

CLK_IN#

I, DIF

Differential Complementary input

5

VDD

Power

Core power supply

6

VDD_O

Power

Power supply for outputs

7

GND_O

Power

Ground for outputs

8

DIF_3#

O, DIF

0.7 V Differential Complementary Output

9

DIF_3

O, DIF

0.7 V Differential True Output

10

DIF_2#

O, DIF

0.7 V Differential Complementary Output

11

DIF_2

O, DIF

0.7 V Differential True Output

12

GND_O

Power

Ground for outputs

13

GND

Power

Ground

14

IREF

I

A precision resistor is attached to this pin to set the differential output current.

W, 1% for 100 W trace, with 50 W termination.

W, 1% for 85 W trace, with 43 W termination.

15

OE0#

I

, SE

LVTTL / LVCMOS active low input for enabling output DIF_0/0#. 0 enables outputs, 1

disables outputs. Internal pull down.

16

OE1#

I

, SE

LVTTL / LVCMOS active low input for enabling output DIF_1/1#. 0 enables outputs, 1

disables outputs. Internal pull down.

17

OE2#

I

, SE

LVTTL / LVCMOS active low input for enabling output DIF_2/2#. 0 enables outputs, 1

disables outputs. Internal pull down.

18

GND

Power

Ground

19

GND_O

Power

Ground for outputs

20

DIF_0

O, DIF

0.7 V Differential True Output

21

DIF_0#

O, DIF

0.7 V Differential Complementary Output

22

DIF_1

O, DIF

0.7 V Differential True Output

23

DIF_1#

O, DIF

0.7 V Differential Complementary Output

24

GND_O

Power

Ground for outputs

EP

Exposed

Pad

Thermal

The Exposed Pad (EP) on the QFN24 package bottom is thermally connected to the die

for improved heat transfer out of package. The exposed pad must be attached to a

heat−sinking conduit. The pad is electrically connected to the die, and must be electri-

cally and thermally connected to GND on the PC board.