NB3H5150

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4

Table 1. PIN DESCRIPTION

Pin

Description

I/O

Name

32

CLK_XTAL1

Crystal or

LVTTL/LVCMOS

or LVPECL/LVDS

Input

Crystal Input or Single−Ended or Differential Clock Input; If CLK_XTAL1 is used as

single−ended input, CLK_XTAL2 must be connected to ground. See Table 2.

EP

Exposed Pad

Ground

Ground – Negative Power Supply is connected via the Exposed Pad .

The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the die

for improved heat transfer out of package. The exposed pad must be attached to a heat

sinking conduit. The pad is electrically connected to the die,carries all power supply return

currents and must be electrically connected to GND.

1. All VDD, AVDDn, VDDOn, EP (GND) pins must be externally connected to a power supply for proper operation. VDD and AVDDn must all

be at the same voltage.

NB3H5150 BASIC OPERATION

Introduction

The NB3H5150 is a Multi−Rate Clock Generator. The

clock reference for the PLL can be either a 25 MHz crystal,

single−ended LVCMOS or LVTTL signal or a differential

LVPECL, LVDS or HCSL signal.

There are two modes of operation for the NB3H5150,

In the Pin−Strap Mode, the user can select any of the

defined output frequencies for each of the four output banks

as specified in Tables 3 and 4 via the three−level Frequency

Select pins: FS1, FS2, FS3, FS4A and FS4B.

register files in Table 5. Each register file is an expanded

selection of output frequencies and level combinations,

output enable/disable and bypass mode functions.

CLKnA & CLKnB − Output Frequency and Output

Level Selection

There are four output banks: CLK1A&B, CLK2A&B and

CLK3A&B are integer only divider outputs, whereas

CLK4A&B can be set or programmed as an integer or

fractional divider.

The output levels for each output bank can be LVPECL

(differential) or LVCMOS (two single−ended). Output

CLK1, 2, 3 and 4 outputs are not phase−aligned, in PLL

or PLL bypass modes.

Power−On Output Default

Upon power−up, all four outputs will be forced to and held

at static LVPECL levels (CLKnA = Low, CLKnB = High)

until the PLL is stable. The PLL will be stable before any of

the output Clocks, CLKnx, are enabled.

SDA & SCL/PD - Serial Data Interface – I2C

The NB3H5150 incorporates a two−wire Serial Data

Interface to expand the flexibility and function of the

NB3H5150 clock generator.

register files into the NB3H5150.

These register files will configure the internal registers to

achieve an expanded selection of output frequencies and

levels combinations for each of the four output blocks.

Subsequent changes in the registers can then be performed

with another register file to modify any of the output

frequencies or output modes.

OE, Output Enable

An OE, Output Enable/Disable function is available only

individual output bank can be enabled or disabled. In

LVCMOS modes outputs will disable LOW for CLKnA and

CLKnB, while the LVPECL mode outputs will disable

CLKnA = Low and CLKnB = High.

Mixed Mode Control (MMC)

control the CLK(n) outputs’ function as defined in Table 7.

REFMODE – Select a Crystal or External Clock Input

Interface (See Table 2)

The REFMODE pin will select the reference input for the

CLK_XTAL1 and CLK_XTAL2 pins to use either a crystal,

an overdriven single−ended or differential input.

When using a crystal, set the REFMODE pin to a LOW.

The CLK_XTAL1 and CLK_XTAL2 input pins will accept

a 25 MHz crystal.

When using a direct−coupled differential input, set the

REFMODE pin to a HIGH.