NB3H5150_16 datasheet(17/19 Pages) ONSEMI

Part #	NB3H5150

Description	2.5V / 3.3V Low Noise Multi-Rate Clock Generator

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Manufacturer	ONSEMI [ON Semiconductor]

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NB3H5150

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17

Interfacing from 2.5 V LVPECL to LVDS

Provided that the LVDS receiver can tolerate large input

voltage peak to peak amplitude, the 2.5 V LVPECL output

can be directly interfaced to an LVDS receiver using proper

ECL termination. The 2.5 V LVPECL output will be able to

drive an LVDS receiver with or without internal 100

W

termination resistor. (See Figures 14, 15 and 16).

Figure 14. Interfacing 2.5 V LVPECL to LVDS with

External 100

W Termination Resistor

RT

100

W

LVPECL

2.5 V

VCC

RE

RE’

LVDS

ZO

Figure 15. Interfacing 2.5 V LVPECL to LVDS with

Internal 100

W Termination Resistor

RT

100

W

LVPECL

2.5 V

VCC

RE

RE’

LVDS

ZO

Figure 16. PSPICE Simulation Levels of 2.5V LVPECL

to LVDS Interface with Example Resistor Values

1.50 V

0.78 V

720 mV

LVDS

Input

2.5 V LVPECL

Output

Where RE = 75 W

Furthermore, a series termination can be used to reduce

the amplitude of the signal as described in AND8020

application note, by placing RS resistor between the driver

and the transmission line. (See Figures 17, 18 and 19).

Figure 17. Interfacing 2.5 V LVPECL to LVDS with

Series RS and External 100 W Termination Resistor

RT

100

W

LVPECL

2.5 V

VCC

RE

RE’

LVDS

ZO

RS

RS’

Figure 18. Interfacing 2.5 V LVPECL to LVDS with

Series RS and Internal 100 W Termination Resistor

LVPECL

2.5 V

VCC

RE

LVDS

ZO

RS

RT

100

W

Figure 19. PSPICE Simulation Levels of 2.5V LVPECL

to LVDS Interface with Series RS Resistor

1.30 V

0.87 V

430 mV

LVDS

Input

2.5 V LVPECL

Output

Where RE = 75 W

RS = 43 W

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NB3H5150 Datasheet(PDF) 17 Page - ON Semiconductor

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