XRT91L33A

3

REV. 1.0.1

STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT

FEATURES......................................................................................................................... 1

APPLICATIONS ................................................................................................................. 1

GENERAL DESCRIPTION................................................................................................. 1

FIGURE 1. BLOCK DIAGRAM OF XRT91L33A..................................................................................................................................... 1

CLOCK AND DATA RECOVERY OVERVIEW ....................................................................................................... 2

FIGURE 2. 20 PIN TSSOP OF XRT91L33A (TOP VIEW)................................................................................................................... 2

TABLE 1: ORDERING INFORMATION.................................................................................................................................................... 2

1.0 PIN DESCRIPTIONS .............................................................................................................................. 4

TABLE 2: PIN DESCRIPTION TABLE .................................................................................................................................................... 4

2.0 FUNCTIONAL DESCRIPTION ............................................................................................................... 6

2.1 REFERENCE CLOCK INPUT ........................................................................................................................... 6

2.2 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................... 6

2.3 EXTERNAL RECEIVE LOOP FILTER CAPACITOR ....................................................................................... 6

2.4 STS-12/STM-4 AND STS-3/STM-1 MODE OF OPERATION ........................................................................... 6

2.5 SIGNAL DETECTION ....................................................................................................................................... 6

FIGURE 3. CONTROL DIAGRAM FOR SIGNAL DETECTION CIRCUIT AND PLL TEST OPERATION ............................................................. 7

2.6 LOCK DETECTION ........................................................................................................................................... 7

2.7 TEST PIN OPERATION .................................................................................................................................... 7

TABLE 3: SIGNAL DETECT AND TEST PIN OPERATION CONTROL........................................................................................................ 8

3.0 ELECTRICAL CHARACTERISTICS ..................................................................................................... 9

3.1 ABSOLUTE MAXIMUM RATINGS ................................................................................................................... 9

TABLE 4: ABSOLUTE MAXIMUM RATINGS............................................................................................................................................ 9

3.2 OPERATING CONDITIONS .............................................................................................................................. 9

TABLE 5: RECOMMENDED OPERATING CONDITIONS ........................................................................................................................... 9

3.3 LVPECL SINGLE ENDED INPUT AND OUTPUT DC CHARACTERISTICS .................................................. 9

TABLE 6: LVPECL SINGLE ENDED INPUTS AND OUTPUTS.................................................................................................................. 9

3.4 LVPECL DIFFERENTIAL INPUT AND OUTPUT DC CHARACTERISTICS ................................................. 10

TABLE 7: LVPECL DIFFERENTIAL INPUTS AND OUTPUTS ................................................................................................................. 10

FIGURE 4. DIFFERENTIAL VOLTAGE SWING DEFINITIONS (INPUT OR OUTPUT) FOR CLOCK AND DATA .................................................... 10

TABLE 8: LVDS OUTPUTS............................................................................................................................................................... 10

TABLE 9: LVTTL INPUTS................................................................................................................................................................. 11

3.5 AC CHARACTERISTICS ................................................................................................................................ 11

TABLE 10: PERFORMANCE SPECIFICATIONS ..................................................................................................................................... 11

4.0 JITTER PERFORMANCE .................................................................................................................... 12

4.1 SONET JITTER REQUIREMENTS ................................................................................................................. 12

4.1.1 RX JITTER TOLERANCE: .......................................................................................................................................... 12

FIGURE 5. GR-253/G.783 JITTER TOLERANCE MASK ...................................................................................................................... 12

FIGURE 6. XRT91L33A JITTER TOLERANCE AT 155 MBPS OC3/STM-1 LOW BANDWIDTH ............................................................. 13

FIGURE 7. XRT91L33A JITTER TOLERANCE AT 155 MBPS OC3/STM-1 HIGH BANDWIDTH ............................................................ 13

FIGURE 8. XRT91L33A JITTER TOLERANCE AT 622 MBPS OC12/STM-4 LOW BANDWIDTH ........................................................... 14

FIGURE 9. XRT91L33A JITTER TOLERANCE AT 622 MBPS OC12/STM-4 HIGH BANDWIDTH .......................................................... 14

4.1.2 JITTER GENERATION................................................................................................................................................ 14

4.1.3 JITTER TRANSFER .................................................................................................................................................... 15

FIGURE 10. XRT91L33A JITTER TRANSFER AT 155 MBPS OC3/STM-1 LOW BANDWIDTH ............................................................. 15

5.0 HIGH-SPEED OUTPUTS ..................................................................................................................... 16

FIGURE 12. HIGH SPEED OUTPUTS, LVDS TERMINATION................................................................................................................. 16

FIGURE 13. HIGH-SPEED OUTPUTS, LVPECL TERMINATION OPTIONS .............................................................................................. 16

6.0 RESAMPLED DATA AND CLOCK OUTPUTS ................................................................................... 17

FIGURE 14. OUTPUT DATA AND CLOCK AFTER RESAMPLING............................................................................................................. 17

TABLE 11: OUTPUT TIMING ............................................................................................................................................................. 17

7.0 PACKAGE DIMENSIONS .................................................................................................................... 18

TABLE 12: REVISION HISTORY......................................................................................................................................................... 18