XRT91L33A

2

STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT

REV. 1.0.1

CLOCK AND DATA RECOVERY OVERVIEW

The clock and data recovery (CDR) unit accepts high speed NRZ serial data from the Differential receiver and

generates a clock with a frequency equal to that of the incoming data. The CDR block uses a reference clock to

train and monitor its clock recovery PLL. Upon startup, the PLL locks to the local reference clock. Once this is

achieved, the PLL attempts to lock onto the incoming receive serial data stream. Whenever the recovered

clock frequency deviates from the local reference clock frequency by more than approximately ±500 ppm, the

clock recovery PLL will switch and lock back onto the local reference clock and declare a Loss of Lock.

Whenever a Loss of Lock or a Loss of Signal event occurs, the CDR will continue to supply a recovered clock

(based on the local reference) to the framer/mapper device. An LOS condition occurs when either SIGD or

LCKTOREFN is low. In this case, the receive serial data output is forced to a logic zero state for the entire

duration of the LOS condition. This acts as a receive data mute upon LOS function to prevent random noise

from being misinterpreted as valid incoming data. When SIGD becomes active again, the recovered clock is

determined to be within ±500 ppm accuracy with respect to the local reference source and LOS is no longer

declared, the clock recovery PLL will switch and lock back onto the incoming receive serial data stream.

XRT91L33AIG-F

20-Pin TSSOP Lead-Free Package

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VDDA

RXDIP

RXDIN

VSSA

LOCK

STS12_MODE

REFCK

LCKTOREFN

VSS

VDD

VDDA

VSSA

CAP+

CAP-

TEST

SIGD

RXDOP

RXDON

RXCLKOP

RXCLKON