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XR1009IST5X Datasheet(PDF) 11 Page - Exar Corporation |
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XR1009IST5X Datasheet(HTML) 11 Page - Exar Corporation |
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11 / 16 page  © 2014 Exar Corporation 11 / 16 exar.com/XR1009 Rev 1B XR1009, XR2009 Layout Considerations General layout and supply bypassing play major roles in high frequency performance. Exar has evaluation boards to use as a guide for high frequency layout and as an aid in device testing and characterization. Follow the steps below as a basis for high frequency layout: ■ Include 6.8µF and 0.1µF ceramic capacitors for power supply decoupling ■ Place the 6.8µF capacitor within 0.75 inches of the power pin ■ Place the 0.1µF capacitor within 0.1 inches of the power pin ■ Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance ■ Minimize all trace lengths to reduce series inductances Refer to the evaluation board layouts below for more information. Evaluation Board Information The following evaluation boards are available to aid in the testing and layout of these devices: Evaluation Board # Products CEB002 XR1009 in TSOT CEB003 XR1009 in SOIC CEB006 XR2009 in SOIC CEB010 XR2009 in MSOP Evaluation Board Schematics Evaluation board schematics and layouts are shown in Figures 9-18 These evaluation boards are built for dual- supply operation. Follow these steps to use the board in a single-supply application: 1. Short -VS to ground. 2. Use C3 and C4, if the -VS pin of the ampli er is not directly connected to the ground plane. Figure 9. CEB002 & CEB003 Schematic Figure 10. CEB002 Top View |
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