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SY89830UK4I Datasheet(PDF) 2 Page - Micrel Semiconductor |
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SY89830UK4I Datasheet(HTML) 2 Page - Micrel Semiconductor |
2 / 10 page 2 Precision Edge™ SY89830U Micrel M9999-111794 hbwhelp@micrel.com or (408) 955-1690 TRUTH TABLE(1) IN0 IN1 IN_SEL /EN Q LX L L L HX L L H XL H L L XH H L H XL H L XH H L Note: 1. = negative edge Pin Number Pin Name Pin Function 1, 2, 3, 4, Q0 to Q3 (LV)PECL, (LV)ECL differential outputs: Terminate with 50 Ω to V CC–2V. For 5, 6, 7, 8 /Q0 to /Q3 single-ended applications, terminate the unused output with 50 Ω to V CC–2V. 9V EE Negative Power Supply: For LVPECL, PECL applications, connect to GND. 10 IN_SEL (LV)PECL, (LV)ECL compatible 2:1 mux input signal select: When IN_SEL is LOW, the IN0 input pair is selected. When IN_SEL is HIGH, the IN1 input pair is selected. Includes a 75k Ω pull-down. Default state is LOW and IN0 is selected. 11, 12, 13, 14 IN0, /IN0 (LV)PECL, (LV)ECL, HSTL clock or data inputs. IN1, /IN1 Internal 75k Ω pull-down resistors on IN0, IN1. Internal 75kΩpull-up and 75kΩ pull-down resistors on /IN0, /IN1. /IN0, /IN1 default condition is V CC/2 when left floating. IN0, IN1 default condition is LOW when left floating. 15 /EN (LV)PECL, (LV)ECL compatible synchronous enable: When /EN goes HIGH, QOUT will go LOW and /QOUT will go HIGH on the next LOW input clock transition. Includes a 75kΩ pull-down. Default state is LOW when left floating. The internal latch is clocked on the falling edge of the input (IN0, IN1) 16 V CC Positive Power Supply: Bypass with 0.1 µF//0.01µF low ESR capacitors. PIN DESCRIPTION |
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