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SN74LVCE161284DLR Datasheet(PDF) 1 Page - Texas Instruments |
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SN74LVCE161284DLR Datasheet(HTML) 1 Page - Texas Instruments |
1 / 14 page SN74LVCE161284 19BIT IEEE 1284 TRANSLATION TRANSCEIVER WITH ERRORFREE POWER UP SCES541 − JANUARY 2004 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Auto-Power-Up Feature Prevents Printer Errors When Printer Is Turned On, But No Valid Signal Is at A9−A13 Pins D 1.4-kΩ Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors D Designed for the IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications D Flow-Through Architecture Optimizes PCB Layout D Ioff and Power-Up 3-State Support Hot Insertion D Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II D ESD Protection − ±4 kV − Human-Body Model − ±8 kV − IEC 61000-4-2, Contact Discharge (Connector Pins) − ±15 kV − IEC 61000-4-2, Air-Gap Discharge (Connector Pins) − ±15 kV − Human-Body Model (Connector Pins) description/ordering information The SN74LVCE161284 is designed for 3-V to 3.6-V VCC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. This device has eight bidirectional bits; data can flow in the A-to-B direction when the direction-control input (DIR) is high and in the B-to-A direction when DIR is low. This device also has five drivers that drive the cable side, and four receivers. The SN74LVCE161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING SSOP − DL Tube SN74LVCE161284DL LVCE161284 0 °C to 70°C SSOP − DL Tape and reel SN74LVCE161284DLR LVCE161284 0 C to 70 C TSSOP − DGG Tape and reel SN74LVCE161284DGGR LVCE161284 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright 2004, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DGG OR DL PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 HD A9 A10 A11 A12 A13 VCC A1 A2 GND A3 A4 A5 A6 GND A7 A8 VCC PERI LOGIC IN A14 A15 A16 A17 HOST LOGIC OUT DIR Y9 Y10 Y11 Y12 Y13 VCC CABLE B1 B2 GND B3 B4 B5 B6 GND B7 B8 VCC CABLE PERI LOGIC OUT C14 C15 C16 C17 HOST LOGIC IN PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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