FEDR27V6441L-002-03

MR27V6441L / P2ROM

TIMING CHART (READ CYCLE)

Serial Data Input/Output Timing

Incorrect command makes this LSI become and keep standby mode until next #CS rising edge. In standby mode,

SO pin is High-Z.

SI

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

SI

SCLK

#CS

Standby Timing

SO

Hi-Z

1

Standby

Standby

#CS

SO

BIT 7

BIT 6

BIT 0

BIT 7

BIT 0

BIT 6

SCLK

SI

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