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FEDL7396ABE-07 Datasheet(PDF) 10 Page - LAPIS Semiconductor Co., Ltd. |
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FEDL7396ABE-07 Datasheet(HTML) 10 Page - LAPIS Semiconductor Co., Ltd. |
10 / 140 page FEDL7396A/B/E-07 ML7396A/B/E 10/140 ●Recommended operating conditions Item Symbol Conditions Min Typ Max Unit Power Supply (I/O) VDDIO VDD_IO, VDD_REG pins 1.8 3.3 3.6 V VDD_PA pin TX power 1mW mode 1.8 3.3 3.6 V VDD_PA pin TX power 10mW mode 2.3 3.3 3.6 V Power Supply (PA) VDDPA VDD_PA pin TX power 20mW mode 2.6 3.3 3.6 V Power Supply (RF) (*2) VDDRF VDD_RF, VDD_IF, VDD_VCO, VDD_CP pins 1.4 1.5 1.6 V Operating Temperature Ta - -40 +25 +85 ˚C Digital Input Rising Time TIR Digital input pins (*1) - - 20 ns Digital Input Falling Time TIF Digital Input pins (*1) - - 20 ns Digital Output Loads CDL All Digital Output pins - - 20 pF Master Clock1 Accuracy (Crystal) FMCK1 XIN, XOUT pins -20ppm (*3) 36 +20ppm (*3) MHz Master Clock2 Accuracy (TCXO) FMCK2 TCXO pin -20ppm (*3) 36 +20ppm (*3) MHz TCXO Input Voltage VTCXO DC cut 0.8 - 1.5 Vpp SPI clock frequency FSCLK SCLK pin 0.032 2 16 MHz SPI clock duty ratio DSCLK SCLK pin 45 50 55 % RF channel frequency FRF LNA_P,PA_OUT pins 863 - 960 MHz *1 Those pins with symbol I, Is at pin definition section *2 Use REG_OUT output of this LSI. *3 It’s max.+10ppm and min.-10ppm at 10kbps setting. [Note] Electrical characteristics are in the above recommended operating conditions without special instruction. |
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