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FEDL7202-001-01 Datasheet(PDF) 9 Page - LAPIS Semiconductor Co., Ltd. |
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FEDL7202-001-01 Datasheet(HTML) 9 Page - LAPIS Semiconductor Co., Ltd. |
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9 / 65 page  FEDL7202-001-01 ML7202-001 9/65 Pin Symbol I/O PDN/RST =”0” Description 38 PCMLNO1 O Hi-Z PCM data output pin of line echo canceler of channel 1. The PCM data is output serially starting from MSB, synchronized to the rising edges of BCLKL and SYNCL. The pin gets in a high impedance state except when the 8-bit PCM data is being output. Also during power-down reset and initial mode, the pin is put in a high impedance. During an end-to-end 4-bit ADPCM transparent mode defined by CR2-B5 (DTHR1) set to “1”, this pin is configured as 4-bit ADPCM data output, and the line echo canceler, the VOX function, and the tone detector are disabled. The 4-bit ADPCM input data from the input pin set by CR0-B3 (IOSEL) is output as it is from this pin. The pin gets in a high impedance state except when the 4-bit ADPCM data is being output. Note that the pin is not configured as an 8-bit PCM data output when CR2-B5 (DTHR1) is set to “1” even if CR2-B7 (CONTA1) is set to “1”. 39 PCMLNO2 O Hi-Z PCM data output pin of line echo canceler of channel 2. The PCM data is output serially starting from MSB, synchronized to the rising edges of BCLKL and SYNCL. The pin gets in a high impedance state except when the 8-bit PCM data is being output. Also during power-down reset and initial mode, the pin is put in a high impedance. During an end-to-end 4-bit ADPCM transparent mode defined by CR3-B5 (DTHR2) set to “1”, this pin is configured as 4-bit ADPCM data output, and the line echo canceler, the VOX function, and the tone detector are disabled. The 4-bit ADPCM input data from the input pin set by CR0-B3 (IOSEL) is output as it is from this pin. The pin gets in a high impedance state except when the 4-bit ADPCM data is being output. Note that the pin is not configured as an 8-bit PCM data output when CR3-B5 (DTHR2) is set to “1” even if CR3-B7 (CONTA2) is set to “1”. 40 TSTI9 I I Input pin for testing. Fix this pin to “0”. 41 PCMLNI1 I I PCM data input pin of line echo canceler of channel 1. This PCM input signal is shifted on the falling edge of BCLKL and is input starting from MSB. The start of PCM data (MSB) is identified by the rising edge of SYNCL. When CR2-B5 (DTHR1) is set to “1”, the pin is configured as a 4-bit ADPCM data input and the input data from this pin is output as it is to the output pin set by CR0-B3 (IOSEL). 42 PCMLNI2 I I PCM data input pin of line echo canceler of channel 2. This PCM input signal is shifted on the falling edge of BCLKL and is input starting from MSB. The start of PCM data (MSB) is identified by the rising edge of SYNCL. When CR3-B5 (DTHR2) is set to “1”, the pin is configured as a 4-bit ADPCM data input and the input data from this pin is output as it is to the output pin set by CR0-B3 (IOSEL). 43 PCMACI1 I I PCM data input pin of line echo canceler of channel 1. This pin is enabled when CR0-B3 (IOSEL) is set to “1” and when CR0-B3 is set to “0”, input to the pin is disabled. When the input is disabled, fix the pin to “0” or “1”. The PCM input signal is shifted on the rising edge of BCLKL and is input starting from MSB. The start of PCM data (MSB) is identified by the rising edge of SYNCL. When CR2-B5 (DTHR1) is set to “1”, the pin is configured as a 4-bit ADPCM data input and 4-bit ADPCM data input from the PCMLNO1 is output from this pin as it is. 44 PCMACI2 I I PCM data input pin of line echo canceler of channel 2. This pin is enabled when CR0-B3 (IOSEL) is set to “1” and when CR0-B3 is set to “0”, input to the pin is disabled. When the input is disabled, fix the pin to “0” or “1”. The PCM input signal is shifted on the rising edge of BCLKL and is input starting from MSB. The start of PCM data (MSB) is identified by the rising edge of SYNCL. When CR3-B5 (DTHR2) is set to “1”, the pin is configured as a 4-bit ADPCM data input and 4-bit ADPCM data input from the PCMLNO2 is output from this pin as it is. |
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