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ML7202-001 Datasheet(PDF) 6 Page - LAPIS Semiconductor Co., Ltd.

Part # ML7202-001
Description  2-Channel Echo Canceler with Multifunction ADPCM Transcoder
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Manufacturer  LAPIS [LAPIS Semiconductor Co., Ltd.]
Direct Link  http://www.lapis-semi.com/
Logo LAPIS - LAPIS Semiconductor Co., Ltd.

ML7202-001 Datasheet(HTML) 6 Page - LAPIS Semiconductor Co., Ltd.

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ML7202-001
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Pin
Symbol
I/O
PDN/RST
=”0”
Description
24
TSTI8
I
I
Input pin for testing. Fix this pin to “0”.
25
BCLKA
I
I
Shift clock input pin for ADPCM data (IS1, IS2, IR1, and IR2). The
frequency is within the range of 64 to 2048 kHz.
26
SYNCA
I
I
8 kHz synchronous signal input pin for ADPCM data. This signal must
be synchronized with the BCLKA signal. This signal indicates the
location of MSB of ADPCM data.
27
IR1
I
I
4-bit ADPCM data input pin on the receive side of channel 1. The
signal that is input to this pin is output to the PCMADO1 pin when
CR0-B3 (IOSEL) is set to “1” and the signal is output to the PCMLNO1
pin when CR0-B3 is set to “0”. This ADPCM data is shifted on the
falling edge of BCLKA, synchronized to SYNCA and input serially
starting from MSB.
When CR2-B7 (CONTA1) is set to “1”, this pin is configured as an 8-bit
PCM data input and the data is processed skipping the ADPCM
transcoder. When CR2-B5 (DTHR1) is set to “1”, the output pin set by
CR0-B3 (IOSEL) is configured as a 4-bit ADPCM data output and the
4-bit ADPCM input data is output as it is.
When CR2-B5 (DTHR1) is set to “1”, the MUTE function is disabled
and, even if CR2-B7 (CONTA1) is set to “1”, the pin is not configured
as an 8-bit PCM data input.
28
IR2
I
I
4-bit ADPCM data input pin on the receive side of channel 2. The
signal that is input to this pin is output to the PCMADO2 pin when
CR0-B3 (IOSEL) is set to “1” and the signal is output to the PCMLNO2
pin when CR0-B3 is set to “0”. This ADPCM data is shifted on the
falling edge of BCLKA, synchronized to SYNCA and input serially
starting from MSB.
When CR3-B7 (CONTA2) is set to “1”, this pin is configured as an 8-bit
PCM data input and the data is processed skipping the ADPCM
transcoder. When CR3-B5 (DTHR2) is set to “1”, the output pin set by
CR0-B3(IOSEL) is configured as a 4-bit ADPCM data output and the
4-bit ADPCM input data is output as it is.
When CR3-B5 (DTHR2) is set to “1”, the MUTE function is disabled,
and even if CR3-B7 (CONTA2) is set to “1”, the pin is not configured as
an 8-bit PCM data input.
29
IS1
O
Hi-Z
ADPCM data output pin on the transmit side of channel 1. When
CR0-B3 (IOSEL) is set to “1”, the signal that is input from the
PCMADI1 pin is output from this pin. When CR0-B3 is set to “0”, the
signal that is input from the PCMLNII1 pin is output. ADPCM data is
output serially starting from MSB, synchronized to the rising edges of
BCLKA and SYNCA, and this pin gets in a high impedance state
except when the 4-bit ADPCM data is being output.
Also during power-down/reset and initial mode, this pin is put in a high
impedance state.
When CR2-B7 (CONTA1) is set to “1”, this pin is configured as an 8-bit
PCM data output skipping the ADPCM transcoder. This pin gets in a
high impedance state except when the 8-bit PCM data is being output.
When CR2-B5 (DTHR1) is set to “1”, the 4-bit ADPCM input data from
the input pin set by CR0-B3 (IOSEL) is output from this pin as it is.
This pin gets in a high impedance state except when the 4-bit ADPCM
data is being output. When CR2-B5 (DTHR1) is set to “1”, the MUTE
function is disabled, and the pin is not configured as an 8-bit PCM data
output even if CR2-B7 (CONTA1) is set to “1”.


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