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ML7202-001 Datasheet(PDF) 10 Page - LAPIS Semiconductor Co., Ltd.

Part # ML7202-001
Description  2-Channel Echo Canceler with Multifunction ADPCM Transcoder
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Manufacturer  LAPIS [LAPIS Semiconductor Co., Ltd.]
Direct Link  http://www.lapis-semi.com/
Logo LAPIS - LAPIS Semiconductor Co., Ltd.

ML7202-001 Datasheet(HTML) 10 Page - LAPIS Semiconductor Co., Ltd.

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FEDL7202-001-01
ML7202-001
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Pin
Symbol
I/O
PDN/RST
=”0”
Description
45
PCMADI1
I
I
PCM data input pin of channel 1. When CR0-B3 (IOSEL) is set to ”1”,
input to this pin is enabled; and when CR0-B3 is set to “0”, input to the
pin is disabled. When the pin input is disabled, fix the pin to “0” or “1”.
The PCM input signal is shifted on the falling edge of BCLKL and is
input starting from MSB.
The beginning of PCM data (MSB) is
identified by the rising edge of SYNCL. When CR2-B5 (DTHR1) is set
to “1”, the pin is configured as a 4-bit ADPCM data input and the 4-bit
ADPCM data input from this pin is output to the IS1 pin as it is. When
CR2-B7 (CONTA1) is set to “1”, the ADPCM transcoder goes into a
through mode and 8-bit PCM data input from this pin is output to the
IS1 pin as it is.
46
PCMADI2
I
I
PCM data input pin of channel 2. When CR0-B3 (IOSEL) is set to ”1”,
input to this pin is enabled; and when CR0-B3 is set to “0”, input to the
pin is disabled. When the pin input is disabled, fix the pin to “0” or “1”.
The PCM input signal is shifted on the falling edge of BCLKL and is
input starting from MSB.
The beginning of PCM data (MSB) is
identified by the rising edge of SYNCL. When CR3-B5 (DTHR2) is set
to “1”, the pin is configured as a 4-bit ADPCM data input and the 4-bit
ADPCM data input from this pin is output to the IS2 pin as it is. When
CR3-B7 (CONTA2) is set to “1”, the ADPCM transcoder goes into a
through mode and 8-bit PCM data input from this pin is output to the
IS2 pin as it is.
47
BCLKL
I
I
Shift clock input pin for PCM data (PCMLNO1/PCMLNI1, PCMACO1
/PCMACI1, PCMADO1/PCMADI1, PCMLNO2/PCMLNI2, PCMACO2
/PCMACI2, and PCMADO2/PCMADI2).
The input frequency is 64 to 2048 kHz.
48
SYNCL
I
I
8 kHz synchronous signal input pin for PCM data. This signal must be
synchronized to the BCLKL signal.
49
TSTI0
I
I
Input pin for testing. Fix this pin to “0”.
50
MTYPE
I
I
Microcontroller interface select pin. When the pin is set to “0”, the pin
is in read/write independent control mode; and when it is set to “1”, the
pin is in read/write shared (R/W) control mode.
When this pin is set to “1”, fix the RD pin to “1”.
51
TSTI1
I
I
52
TSTI2
I
I
53
TSTI3
I
I
54
TSTI4
I
I
55
TSTI5
I
I
Input pins for LSI manufacturer’s testing. Fix these pins to “0”.
56
A0
I
I
57
A1
I
I
58
A2
I
I
59
A3
I
I
60
A4
I
I
Address input pins for accessing the control register
61
VBG
O
About
1.2 V
Regulator reference voltage output pin. The output voltage is about
1.2 V.
Connect a 150 pF bypass capacitor between this pin and the DGND1
pin.
62
DVDD1
+3.3 V digital power supply pin
63
VOUT1
O
About
2.6 V
Regulator output pin. The output voltage is about 2.6 V.
Connect 10
F and 0.1 F bypass capacitors between this pin and the
DGND1 pin.
64
TSTI6
I
I
Input pin for LSI manufacturer’s testing. Fix this pin to “0”.


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