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ML7202-001 Datasheet(PDF) 8 Page - LAPIS Semiconductor Co., Ltd.

Part # ML7202-001
Description  2-Channel Echo Canceler with Multifunction ADPCM Transcoder
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Manufacturer  LAPIS [LAPIS Semiconductor Co., Ltd.]
Direct Link  http://www.lapis-semi.com/
Logo LAPIS - LAPIS Semiconductor Co., Ltd.

ML7202-001 Datasheet(HTML) 8 Page - LAPIS Semiconductor Co., Ltd.

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FEDL7202-001-01
ML7202-001
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Pin
Symbol
I/O
PDN/RST
=”0”
Description
35
PCMADO2
O
Hi-Z
PCM data output pin of channel 2. This pin is enabled when CR0-B3
(IOSEL) is set to “1” and is put in a high impedance state when
CR0-B3 is set to “0”. The PCM data is output serially starting from
MSB, synchronized to the rising edges of BCLKL and SYNCL, and the
pin gets in a high impedance state except when the 8-bit PCM data is
being output. Also during power-down reset and initial mode, the pin is
also put in a high impedance.
When CR3-B5 (DTHR2) is set to “1”, this pin is configured as a 4-bit
ADPCM data output and 4-bit ADPCM input data itself from the IR2 pin
is output. This pin gets in a high impedance state except when the
4-bit ADPCM data is being output. When CR3-B7 (CONTA2) is set to
“1”, the ADPCM transcoder goes into a through mode and 8-bit PCM
input data from the IR2 pin is output as it is from this pin. The pin gets
in a high impedance state except when the 8-bit PCM data is being
output.
When CR3-B5 (DTHR2) is set to “1”, the MUTE function is disabled
and the pin is not configured as an 8-bit PCM data output even if
CR3-B7 (CONTA2) is set to “1”.
36
PCMACO1
O
Hi-Z
PCM data output pin of channel 1 line echo canceler. This pin is
enabled when CR0-B3 (IOSEL) is set to “1”. When CR0-B3 is set to
“0”, the pin is put in a high impedance. PCM data is output serially
starting from MSB, synchronized to the rising edges of BCLKL and
SYNCL, and the pin gets in a high impedance state except when the
8-bit PCM data is being output. Also during power-down reset and
initial mode, the pin is put in a high impedance.
During an end-to-end 4-bit ADPCM transparent mode defined by
CR2-B5 (DTHR1) set to “1”, this pin is configured as 4-bit ADPCM data
output, and the line echo canceler, the VOX function, and the tone
detector are disabled. The 4-bit ADPCM input data from the PCMLNI1
pin is output as it is, and the pin gets in a high impedance state except
when the 4-bit ADPCM data is being output.
Note that the pin is not configured as an 8-bit PCM data output when
CR2-B5 (DTHR1) is set to “1” even if CR2-B7 (CONTA1) is set to “1”.
37
PCMACO2
O
Hi-Z
PCM data output pin of channel 2 line echo canceler. This pin is
enabled when CR0-B3 (IOSEL) is set to “1”. When CR0-B3 is set to
“0”, the pin is put in a high impedance. PCM data is output serially
starting from MSB, synchronized to the rising edges of BCLKL and
SYNCL, and the pin gets in a high impedance state except when the
8-bit PCM data is being output. Also during power-down reset and
initial mode, the pin is put in a high impedance.
During an end-to-end 4-bit ADPCM transparent mode defined by
CR3-B5 (DTHR2) set to “1”, this pin is configured as 4-bit ADPCM data
output, the VOX function, and the tone detector are disabled. The 4-bit
ADPCM input data from the PCMLNI2 pin is output as it is, and the pin
gets in a high impedance state except when the 4-bit ADPCM data is
being output.
Note that the pin is not configured as an 8-bit PCM data output when
CR3-B5 (DTHR2) is set to “1” even if CR3-B7 (CONTA2) is set to “1”.


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