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SMJ44400HR Datasheet(PDF) 6 Page - Austin Semiconductor |
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SMJ44400HR Datasheet(HTML) 6 Page - Austin Semiconductor |
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6 / 21 page  DRAM SMJ44400 Austin Semiconductor, Inc. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 TIMING REQUIREMENTS (-55oC<T A<125 oC or -40oC to +85oC; Vcc = 5V +10%) SYM PARAMETER MIN MAX MIN MAX MIN MAX UNIT tRC Cycle time, random read or write 1 150 180 210 ns tRWC Cycle time, read-write 205 245 285 ns tPC Cycle time, page-mode read or write 2 50 60 65 ns tPRWC Cycle time, page-mode read-write 100 120 135 ns tRASP Pulse duration, page mode, RAS\ low 3 80 100000 100 100000 120 100000 ns tRAS Pulse duration, nonpage mode, RAS\ low 3 80 10000 100 10000 120 10000 ns tCAS Pulse duration, CAS\ low 4 20 10000 25 10000 30 10000 ns tCP Pulse duration, CAS\ High 10 10 15 ns tRP Pulse duration, RAS\ High (precharge) 60 70 80 ns tWP Pulse duration, write 15 20 25 ns tASC Setup time, column address before CAS\ low 0 0 0 ns tASR Setup time, row address before RAS\ low 0 0 0 ns tDS Setup time, data 5 000 ns tRCS Setup time, read before CAS\ low 0 0 0 ns tCWL Setup time, W\ low before CAS\ high 20 25 30 ns tRWL Setup time, W\ low before RAS\ high 20 25 30 ns tWCS Setup time, W\ low before CAS\ low (early-write operation only) 000 ns tWSR Setup time, W\ High (CBR refresh only) 10 10 10 ns tCAH Hold time, column address after CAS\ low 15 20 20 ns tDHR Hold time, data after RAS\ low 60 75 90 ns tDH Hold time, data 5 15 20 25 ns tAR Hold time, column address after CAS\ low 4 60 75 90 ns tRAH Hold time, row address after RAS\ low 10 15 15 ns tRCH Hold time, read after CAS\ High 6 000 ns tRRH Hold time, read after RAS\ High 6 000 ns tWCH Hold time, write after CAS\ low (early-write operation only) 15 20 25 ns tWCR Hold time, write after RAS\ low 4 60 75 90 ns tWHR Hold time, W\ High (CBR refresh only) 10 10 10 ns tOEH Hold time, OE\ command 20 25 30 ns tROH Hold time, RAS\ referenced to OE\ 20 25 30 ns tAWD Delay time, column address to W\ low (read-write operation only) 70 80 90 ns tCHR Delay time, RAS\ low to CAS\ High (CBR refresh only) 20 20 25 ns tCRP Delay time, CAS\ High to RAS\ low 0 0 0 ns tCSH Delay time, RAS\ low to CAS\ High 80 100 120 ns tCSR Delay time, CAS\ low to RAS\ low (CBR refresh only) 10 10 10 ns tCWD Delay time, CAS\ low to W\ low (read-write operation only) 50 60 70 ns -8 -10 -12 NOTES: 1. All cycle times assume t T = 5ns. 2. To assure t PC min, t ASC should be > t CP . 3. In a read-write cycle, t RWD and t RWL must be observed. 4. In a read-write cycle, t CWD and t CWL must be observed. 5. Referenced to the later of CAS\ or W\ in write operations. 6. Either t RRH or t RCH must be satisfied for a read cycle. |
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