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LM1893 Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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LM1893 Datasheet(HTML) 6 Page - National Semiconductor (TI) |
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6 / 24 page  Application Information THE DATA PATH The BI-LINETM chip serves as a power line interface in the carrier-current transceiver (CCT) system of Figure 3 Figure 4 shows the interface circuit now discussed The controller may select either the transmit (TX) or receive (RX) mode Serial data from the controller is used to generate a FSK- modulated 50 to 300 kHz carrier on the line in the TX mode In the RX mode line signal passes through the coupling transformer into the PLL-based receiver The recreated seri- al bit stream drives the controller With the IC in the TX mode (pin 5 a logic high) baseband data to 5 kHz drive the modulator’s Data In pin to generate a switched 0978I1022I control current to drive the low TC triangle-wave current-controlled oscillator to g22% devia- tion The tri-wave passes through a differential attenuator and sine shaper which deliver a current sinusoid through an automatic level control (ALC) circuit to the gain of 200 cur- rent output amplifier Drive current from the Carrier IO de- velops a voltage swing on T1’s (Figure 4 ) resonant tank proportional to line impedance then passes through the step-down transformer and coupling capacitor CC onto the line Progressively smaller line impedances cause reduced signal swing but never clipping-thus avoiding potential radio frequency interference When large line impedances threat- en to allow excessive output swing on pin 10 the ALC shunts current away from the output amplifier holding the voltage swing constant and within the amp’s compliance limit The amplifier is stable with a load of any magnitude or phase angle In the RX mode (pin 5 a logic low) the TX sections on the chip are disabled Carrier signal broad-band noise transient spikes and power line component impinge of the receiver’s input highpass filter made up of CC and T1 and the tank bandpass filter In-band carrier signal band-limited noise heavily attenuated line frequency component and attenuat- ed transient energy pass through to produce voltage swing on the tank swinging about the positive supply to drive the Carrier IO receiver input The balanced Norton-input limiter amplifier removes DC offsets attenuates line frequency performs as a bandpass filter and limits the signal to drive the PLL phase detector differentially The differential de- modulated output signal from the phase detector contain- ing AC and DC data signal noise system DC offsets and a large twice-the-carrier-frequency component passes through a 3-stage RC lowpass filter to drive the offset can- cel circuit differentially The offset cancelling circuit works by insuring that the (fixed) g50 mV signal delivered to the data squaring (‘‘slicing’’) comparator is centered around the 0 mV comparator switch point Whenever the comparator signal plus DC offset and noise moves outside the carefully matched g50 mV voltage ‘‘window’’ of the offset cancel circuit it adjusts its DC correction voltage in series with the differential signal to force the signal back into the window While the signal is within the g50 mV window the DC offset is stored on capacitor CM By grace of the highly non-linear offset hold capacitor charging during offset cancelling the DC cancellation is done much more quickly than with an AC coupling capacitor normally used in place of the offset can- cel circuit Since impulse noise spikes normally ring the sig- nal symmetrically around 0 V the fully bilateral offset cancel topology affords excellent noise rejection The switched cur- rent output of the comparator drives the impulse noise filter integrator capacitor that rejects all data pulses of less than the integrator charge time Noise appears as duty-cycle jitter at the open collector serial data output Dual-In-Line Package TLH6750 – 2 Top View Order Number LM1893N See NS Package Number N18A Small Outline Dual-In-Line Package TLH6750 – 41 Top View Order Number LM2893M or LM2893N See NS Package Number M20B or N20A FIGURE 2 Connection Diagrams TLH6750 – 3 FIGURE 3 The block diagram of a carrier-current system using the Bi-Line chip to interface digital controllers via the power line Unless otherwise noted all pin references refer to LM1893 but hold true for equivalent LM2893 pin 6 |
Similar Part No. - LM1893 |
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Similar Description - LM1893 |
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