FEDL610Q419-07

ML610Q419/ML610Q419C

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• LCD driver

− Dot matrix can be supported.

ML610Q419

: 192 dots max. (48 seg

× 4 com)

ML610Q419C : 160 dots max. (40 seg

× 4 com)

− 1/1 to 1/4 duty

− 1/2, 1/3 bias (built-in bias generation circuit)

− Frame frequency selecable: approx. 64Hz, 73Hz, 85Hz, and 102Hz

− Bias voltage multiplying clock selectable (8 types)

− LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable

− Programmable display allocation function

• Reset

− Reset by the RESET_N pin

− Reset by power-on detection

− Reset when oscillation stop of the low-speed clock is detected

− Reset by low level detection (LLD)

The voltage which is released from reset is selectable by the code-option: 1.1V, 1.8V (Max.)

• Power supply voltage detect function

− Judgment voltages:

One of 16 levels

− Judgment accuracy:

±2% (Typ.)

• Clock

− Low-speed clock: (This LSI can not guarantee the operation withoug low-speed clock)

Crystal oscillation (32.768 kHz)

− High-speed clock:

Built-in RC oscillation (500kHz)

Built-in PLL oscillation (8.192 MHz

±2.5%), crystal/ceramic oscillation (4.096 MHz), external clock

− Selection of high-speed clock mode by software:

Built-in RC oscillation, built-in PLL oscillation, crystal/ceramic oscillation, external clock

• Power management

− HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states).

− STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are

stopped.)

− Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation

clock)

− Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused peripherals.

• Guaranteed operating range

− Operating temperature: −20°C to 70°C

− Operating voltage: V