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FEDL610Q409-02 Datasheet(PDF) 10 Page - LAPIS Semiconductor Co., Ltd. |
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FEDL610Q409-02 Datasheet(HTML) 10 Page - LAPIS Semiconductor Co., Ltd. |
10 / 34 page FEDL610Q409-05 ML610Q407/ML610Q408/ML610Q409 10/34 ML610Q408 Chip Pin Layout & Dimension Note: The assignment of the pads P30 to P35 are not in order. Chip size: 2.27 mm × 2.23 mm PAD count: 88 pins Minimum PAD pitch: 80 µm PAD aperture: 70 µm×70µm Chip thickness: 350 µm Voltage of the rear side of chip: VSS level. Figure 6 ML610Q408 Chip Layout & Dimension 29 28 27 26 VPP P53 P54 P55 P56 P57 P35 P33 P32 P34 88 P31 87 P30 86 P04 85 P03 84 P02 83 P01 82 P00 81 P24 80 P22 79 P21 78 P20 77 VSS SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 COM4/SEG2 COM3/SEG1 COM2/SEG0 COM1 COM0 C2 C1 32 31 30 35 34 33 38 37 36 41 40 39 44 43 42 25 24 23 73 72 71 70 69 68 75 74 Y X 2.23mm 2.27mm 67 76 |
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