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ADP7159 Datasheet(PDF) 14 Page - Analog Devices |
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ADP7159 Datasheet(HTML) 14 Page - Analog Devices |
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14 / 23 page  Data Sheet ADP7156 Rev. A | Page 13 of 22 THEORY OF OPERATION The ADP7156 is an ultralow noise, high PSRR linear regulator targeting radio frequency (RF) applications. The input voltage range is 2.3 V to 5.5 V, and it can deliver up to 1.2 A of load current. Typical shutdown current consumption is 0.2 µA at room temperature. Optimized for use with 10 µF ceramic capacitors, the ADP7156 provides excellent transient performance. VREG GND (EPAD) VOUT VIN EN REF REF_SENSE VOUT_SENSE REFERENCE SHUTDOWN CURRENT-LIMIT, THERMAL PROTECT OTA BYP INTERNAL REGULATOR Figure 41. Simplified Internal Block Diagram Internally, the ADP7156 consists of a reference, an error ampli- fier, and a P-channel MOSFET pass transistor. The output current is delivered via the PMOS pass device, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to pass and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, allowing less current to pass and decreasing the output voltage. By heavily filtering the reference voltage, the ADP7156 can achieve 1.7 nV/√Hz typical output noise spectral density from 10 kHz to 1 MHz. Because the error amplifier is always in unity gain, the output noise is independent of the output voltage. The ADP7156 uses the EN pin to enable and disable the VOUT pin under normal operating conditions. When EN is high, VOUT turns on, and when EN is low, VOUT turns off. For automatic startup, tie EN to VIN. 4V 7V 4V 4V 4V 4V 4V 4V 4V 4V 7V 7V 4V VIN VREG REF REF_SENSE BYP VOUT VOUT_SENSE EN GND (EPAD) Figure 42. Simplified ESD Protection Block Diagram The ESD protection devices are shown in the block diagram as Zener diodes (see Figure 42). |
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