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PL500-37SC-R Datasheet(PDF) 2 Page - Micrel Semiconductor |
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PL500-37SC-R Datasheet(HTML) 2 Page - Micrel Semiconductor |
2 / 6 page (Preliminary) PL500-37 Low Phase Noise VCXO (36MHz to 130MHz) Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 09/09/05 Page 2 PIN AND PAD ASSIGNMENT AND DESCRIPTION Name Pin# Die Pad Position Type Description SOP-8 SOT23-6 X ( m) Y ( m) XIN 1 3 94.183 768.599 I Crystal input pin. OE 2 - 94.157 605.029 I Output Enable input pin. Disables the output when low. Internal pull-up enables output by default if pin is not connected to low. Use only one OE signal. - - 715.472 626.716 VCON 3 1 94.183 331.756 I Frequency control voltage input pin. GND 4 2 94.193 140.379 P Ground pin. CLK 5 6 715.472 203.866 O Output clock pin. VDD 6 5 715.307 455.726 P VDD power supply pin. Only one VDD pin is necessary. DNC 7 - - - I Do Not Connect. No Internal Connection. XOUT 8 4 476.906 888.881 I Crystal output pin. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage VDD 4.6 V Input Voltage, dc VI -0.5 VDD+0.5 V Output Voltage, dc VO -0.5 VDD+0.5 V Storage Temperature TS -65 150 C Ambient Operating Temperature* TA -40 85 C Junction Temperature TJ 125 C Lead Temperature (soldering, 10s) 260 C ESD Protection, Human Body Model 2 kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended per iods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the dev ice at these or any other conditions above the operational limits noted in this specificatio n is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only. |
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