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A6274KLPTR-T Datasheet(PDF) 11 Page - Allegro MicroSystems |
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A6274KLPTR-T Datasheet(HTML) 11 Page - Allegro MicroSystems |
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11 / 24 page  Linear Current Regulator and Controller for Automotive LED Arrays A6274, A6274-1 A6284, A6284-1 11 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com PWM Dimming in DIM Mode LED dimming during DIM mode can be controlled internally by the A6274/84, or externally. For external PWM mode, connect an external clock pulse on the PWMIN pin, which controls dim- ming, frequency, and duty cycle. The A6274/84 detects the logic level on the PWMIN pin. When logic voltage is applied on the PWMIN pin, the IC switches to external PWM mode where dim- ming, frequency, and duty cycle are directly controlled by signals on PWMIN pin. In internal PWM mode, dimming frequency can be set using a resistor connected from PWMIN pin to GND as shown in Fig- ure 1. It is not necessary to select the PWM mode before startup: the IC will transition from internal to external when PWMIN is raised above VLOGIC(H); and it will transition from external to internal when external PWMIN signal is removed for more than 20 ms. LEDx will not blink; they will be off during this period. The recommended range for PWM frequency is 200 Hz to 2 kHz. Maximum PWM frequency is limited due to acceptable error at minimum PWM duty cycle. At higher PWM frequency and smaller duty cycles, error in LED current increases due to slow ramp-up and ramp-down in LED current. It is recommended to use a minimum on-time > 20 µs. The equation for internal PWM frequency setting with the PWMIN pin resistor is given by: fPWM = (14165 ÷ RFPWM) + 19 where fPWM is in Hz and RFPWM is in kΩ. For example, with a 29.4 kΩ resistor, fPWM = 500 Hz. RFPWM must be greater than 5 kΩ for internal PWM; below this value, the PWMIN pin is detected at a logic-low level and oper- ates in external PWM mode. The voltage on the DR pin determines the operating duty cycle. For better accuracy, derive this voltage from BIAS using a volt- age divider. The PWM duty cycle depends on the ratio of the DR and BIAS pin voltages. The duty cycle can be reduced, down to 5% (see Figure 5), as: PWM (%) = 139 × VDR ÷ VBIAS where VDR and VBIAS are in volts (V). LED Current Setting The peak LED current can be set at up to 60 or 120 mA per chan- nel through the ISETx pin. ISET1 sets current through LED1-3 and ISET2 sets current through LED4-6. By connecting ISET2 to BIAS, ISET1 current can be mirrored on all enabled LED channels (LED1-6). This will improve current matching between LED1-6 when all LED strings are identical. Connect a resistor, RISETx, between ISETx pin and ground, to set peak LED current through each channel. The value of peak LED current through each LEDx sink is given by: ILED(PEAK) = 298 ÷ RISETx (kΩ) for A6274 ILED(PEAK) = 590 ÷ RISETx (kΩ) for A6284 where ILED is in mA and RISETx in kΩ. This sets the peak current through each LEDx, referred as the 100% Current. The average LEDx current can be reduced from the 100% Current value by dimming PWM duty ratio. 0 20 40 60 80 100 00.6 1.2 1.8 2.4 3.0 3.6 VDR (V) Figure 5: Relationship of Voltage on DR pin (VDR) and Dimming Duty Cycle VDR can be varied from 0 to 3.6 V |
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