© 2000 Fairchild Semiconductor Corporation

DS010968

www.fairchildsemi.com

December 1991

Revised May 2000

SCANPSC100F

Embedded Boundary Scan Controller

(IEEE 1149.1 Support)

General Description

The SCANPSC100F is designed to interface a generic par-

allel processor bus to a serial scan test bus. It is useful in

improving scan throughput when applying serial vectors to

system test circuitry and reduces the software overhead

that is associated with applying serial patterns with a paral-

lel processor. The SCANPSC100F operates by serializing

data from the parallel bus for shifting through the chain of

1149.1 compliant components (i.e., scan chain). Scan data

returning from the scan chain is placed on the parallel port

to be read by the host processor. Up to two scan chains

can be directly controlled with the SCANPSC100F via two

independent TMS pins. Scan control is supplied with user

specific patterns which makes the SCANPSC100F proto-

col-independent. Overflow and underflow conditions are

prevented by stopping the test clock. A 32-bit counter is

used to program the number of TCK cycles required to

complete a scan operation within the boundary scan chain

or to complete a SCANPSC100F Built-In Self Test (BIST)

operation. SCANPSC100F device drivers and 1149.1

embedded test application code are available with Fair-

child’s SCAN Ease software tools.

Features

s Compatible with IEEE Std. 1149.1 (JTAG) Test Access

Port and Boundary Scan Architecture

s Supported by Fairchild’s SCAN Ease (Embedded Appli-

cation Software Enabler) Software

s Uses generic, asynchronous processor interface; com-

patible with a wide range of processors and PCLK fre-

quencies

s Directly supports up to two 1149.1 scan chains

s 16-bit Serial Signature Compaction (SSC) at the Test

Data In (TDI) port

s Automatically produces pseudo-random patterns at the

Test Data Out (TDO) port

s Fabricated on FACT

 1.5 µm CMOS process

s Supports 1149.1 test clock (TCK) frequencies up to

25 MHz

s TTL-compatible inputs; full-swing CMOS outputs with

24 mA source/sink capability

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

FACT

 is a trademark of Fairchild Semiconductor Corporation.

Order Number

Package Number

Package Description

SCANPSC100FSC

M28B

28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide