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DSC400-3131Q0001KI2T Datasheet(PDF) 5 Page - Microchip Technology |
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DSC400-3131Q0001KI2T Datasheet(HTML) 5 Page - Microchip Technology |
5 / 20 page 2016 Microchip Technology Inc. DS20005612A-page 5 DSC400 3.0 OPERATIONAL DESCRIPTION The DSC400 is a crystal-less™ clock generator. Unlike older clock generators in the industry, it does not require an external crystal to operate; it relies on the integrated MEMS resonator that interfaces with internal PLLs. This technology enhances performance and reliability by allowing tighter frequency stability over a far wider temperature range. In addition, the higher resistance to shock and vibration decreases the aging rate to allow for much improved product life in the system. 3.1 Inputs There are four input signals in the device. Each has an internal (40 kΩ) pull-up to default the selection to a high (1). Inputs can be controlled through hardware strapping method with a resistor to ground to assert the input low (0). Inputs may also be controlled by other components’ GPIOs In case more than one frequency set is desired, FSB1 and FSB2 are used to independently select one of two sets per bank. FSB1 selects the pre-configured set on Bank1 (CLK0 and CLK3) and FSB2 selects the pre-configured set on Bank2 (CLK1 and CLK2), as shown in Table 1-1 in the Product Identification System section. If there is a requirement to disable outputs, the inputs OE1 and OE2 are used in conjunction to disable the banks of outputs. Outputs are disabled in tri-state (Hi-Z) mode. See Table 3-1 for more information. 3.2 Outputs The four outputs are grouped into two banks. Each bank is supplied by an independent VDD to allow for optimized noise isolation between the two banks. Each bank provides two synchronous outputs generated by a common PLL: • Bank1 is composed of outputs CLK0 and CLK3. • Bank2 is composed of outputs CLK1 and CLK2. Each output may be pre-configured independently to be one of the following formats: LVCMOS, LVDS, LVPECL or HCSL. In case the output is configured to be single-ended LVCMOS, the frequency is generated on the true output (CLKx+) and the complement output (CLKx–) is shut off in a low state. Frequencies can be chosen from 2.3 MHz to 460 MHz for differential outputs and from 2.3 MHz to 170 MHz on LVCMOS outputs. 3.3 Power VDD1 and VDD2 supply the power to banks 1 and 2 respectively. Each VDD may each have a different supply voltage from the other as long as it is within the 2.25V to 3.6V range. Each VDD pin should have a 0.1 µF capacitor to filter high-frequency noise. VSS is common to the entire device. TABLE 3-1: OUTPUT ENABLE SELECTION TABLE OE1 OE2 Bank 1 (CLK0 & CLK3) Bank 2 (CLK1 & CLK2) 0 0 Hi-Z Hi-Z 0 1 Hi-Z Running 1 0 Running Hi-Z 1 1 Running Running |
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