MC100LVEL30

www.onsemi.com

4

−40°C

25°C

85°C

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Maximum Toggle Frequency

1.2

1.2

1.2

GHz

Propagation Delay to Output

CLK, S, R

550

800

570

820

590

840

ps

Setup Time

Hold Time

150

200

0

100

150

200

0

100

150

200

0

100

ps

Set/Reset Recovery

400

200

400

200

400

200

ps

Minimum Pulse Width

CLK

Set, Reset

400

650

400

650

400

650

ps

Cycle-to-Cycle Jitter

TBD

TBD

TBD

ps

Output Rise/Fall Times Q (20%−80%)

280

550

280

450

550

280

550

ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

Figure 2. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D − Termination of ECL Logic Devices)

Driver

Device

Receiver

Device

QD

Q

D

50 W

50 W

Resource Reference of Application Notes

AN1405/D

− ECL Clock Distribution Techniques

AN1406/D

− Designing with PECL (ECL at +5.0 V)

AN1503/D

− ECLinPS I/O SPiCE Modeling Kit

AN1504/D

− Metastability and the ECLinPS Family

AN1568/D

− Interfacing Between LVDS and ECL

AN1672/D

− The ECL Translator Guide

AND8001/D − Odd Number Counters Design

AND8002/D − Marking and Date Codes

AND8020/D − Termination of ECL Logic Devices

AND8066/D − Interfacing with ECLinPS

AND8090/D − AC Characteristics of ECL Devices