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TLV5638MDREP Datasheet(PDF) 11 Page - Texas Instruments

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Part No. TLV5638MDREP
Description  2.7-V TO 5.5V LOW-POWER DUAL 12 BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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TLV5638MDREP Datasheet(HTML) 11 Page - Texas Instruments

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TLV5638EP
2.7V TO 5.5V LOW POWER DUAL 12BIT DIGITALTOANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SGLS130B − JULY 2002 − REVISED DECEMBER 2003
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
serial interface
A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling
edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the
target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word.
Figure 13 shows examples of how to connect the TLV5638 to TMS320, SPI
, and Microwire.
TMS320
DSP FSX
CLKX
DX
TLV5638
SCLK
DIN
CS
SPI
I/O
SCK
MOSI
TLV5638
SCLK
DIN
CS
Microwire
I/O
SK
SO
TLV5638
SCLK
DIN
CS
Figure 13. Three-Wire Interface
Notes on SPI
 and Microwire: Before the controller starts the data transfer, the software has to generate a
falling edge on the pin connected to CS. If the word width is 8 bits (SPI
 and Microwire), two write operations
must be performed to program the TLV5638. After the write operation(s), the holding registers or the control
register are updated automatically on the 16th positive clock edge.
serial clock frequency and update rate
The maximum serial clock frequency is given by:
f
sclkmax +
1
t
whmin ) twlmin
+ 20 MHz
The maximum update rate is:
f
updatemax +
1
16 t
whmin ) twlmin
+ 1.25 MHz
Note, that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the
TLV5638 has to be considered, too.


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